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<h1>usrp_standard_tx Member List</h1>This is the complete list of members for <a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a>, including all inherited members.<table>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a09ce78134eea035e42464123356096e4">_common_write_oe</a>(txrx_t txrx, int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a3814dc28edce07e3b5cb48bb3ebdf244">_read_9862</a>(int which_codec, int regno, unsigned char *value) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad28278c9ff7a33b3a151c561ab037b9f">_read_9862</a>(int which_codec, int regno) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8f92d2e9630ec614eedc61858756cce1">_read_aux_adc</a>(int slot, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a2aadef5c105459794b22a135730e7480">_read_aux_adc</a>(int slot, int which_adc)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4fa26bd8164bd5782adf7fbe00b3d411">_read_fpga_reg</a>(int regno, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#abf1f167a1c96dd0ed4589afc6c9fad6c">_read_fpga_reg</a>(int regno)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9b54622fec87c2ed9c7808078931371f">_read_spi</a>(int optional_header, int enables, int format, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4585f9c7df7084a6acb29bd6d7950892">_set_led</a>(int which_led, bool on)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8a25444c83f59f7517d0ff687d2ff053">_write_9862</a>(int which_codec, int regno, unsigned char value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab8870a35e0bdc63ee6655b5264a6d142">_write_aux_dac</a>(int slot, int which_dac, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac5bdb9be69f27eb3a0530cba9536d0f4">_write_fpga_reg</a>(int regno, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a0c200dc2d39d68d7a77e92859c5228a0">_write_fpga_reg_masked</a>(int regno, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a0ecdfcb63c28d66b2f036156e33f20d8">_write_oe</a>(int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aaf100fafc406ef75faafcf3e38df7849">_write_spi</a>(int optional_header, int enables, int format, std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a3d88f6bddfb24f2ad375b65b935ac6e9">block_size</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a9452b1ce5881965ca36d780f928b6cb6">calc_dxc_freq</a>(double target_freq, double baseband_freq, double fs, double *dxc_freq, bool *inverted)</td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191a55fe460189a049f7aea3f9bc149adf91">CM_NEG_FDAC_OVER_4</a> enum value</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191a98ba952bdb469cbbb02a163216162e7c">CM_NEG_FDAC_OVER_8</a> enum value</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191afd3ae5e29447d64701502467ce0886c7">CM_OFF</a> enum value</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191aad92fc027ad13bcbf3cc8839918822bc">CM_POS_FDAC_OVER_4</a> enum value</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191ad3e2a1cb01acbb2e491780a2ad334e14">CM_POS_FDAC_OVER_8</a> enum value</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4c70322824b7b9d040aa265d0587c191">coarse_mod_t</a> enum name</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a878b5d0c2c3878a27c54eb95122467f9">coarse_modulator</a>(int channel) const </td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac25d56e74572309a87397f0fce1a102b">common_pga</a>(txrx_t txrx, int which_amp) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a06cfd0e5675618f773c5466bd235a369">common_pga_db_per_step</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a7dd5c384b9d2cd4e412939c3b7b7ac79">common_pga_max</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a95453e5bb4d0ed4c05b1ea64c880170a">common_pga_min</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a37bd03473a98cf3776f1988914c1a5ce">common_read_aux_adc</a>(txrx_t txrx, int which_side, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab84d66e92dc16fdc104fae9341f1e64f">common_read_aux_adc</a>(txrx_t txrx, int which_side, int which_adc)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af7e33b5762cd9c80a714806fa6fa2244">common_read_io</a>(txrx_t txrx, int which_side, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a217f6865ef04d1111c2c1d3e7b4260f5">common_read_io</a>(txrx_t txrx, int which_side)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a52f96a90c91ed6e74bfc6a91691a7fa2">common_set_pga</a>(txrx_t txrx, int which_amp, double gain_in_db)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a0997e93568c71e5432c2445b1ebcc991">common_write_atr_mask</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a89eda6a96bc7f4d2d634da793eccbc20">common_write_atr_rxval</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a26e38a0f9f98390b712709812e3387af">common_write_atr_txval</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac7354a9c4f7e961cb1b541c970a8d009">common_write_aux_dac</a>(txrx_t txrx, int which_side, int which_dac, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#acf3120592af4df79d38d253c98c633ae">common_write_io</a>(txrx_t txrx, int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad673bc49b311e29ab01727c5933ea028">common_write_refclk</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a4eefc136417ea3a75a296c1b6dbbd470">converter_rate</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [inline, virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a1d6b6839b9ba385d93684c3497c3fb16">d_bytes_per_poll</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a5c439350ad4d861c49c21d203110eedb">d_coarse_mod</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a747a3cfca6d00b8d2960b4692ae36bc2">d_ctx</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aa45df525ed16ee0c885a4972ac7908b4">d_db</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a686ea66e3f43c9ab6df60bd80f41ac3b">d_dbid</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#afa81d2ee842dd6eef04c422276f52d1d">d_fpga_master_clock_freq</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af3d08c8bcdd0ed116e76ffa5449004f2">d_fpga_shadows</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a4b22d4e7f26f031d01fe99b4c8394447">d_hw_mux</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ac1c7c7ce9479045ad9dca8f409f5ef87">d_interp_rate</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a536872bd7b7f90d94bf58f5b45df0f3d">d_nchan</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#adc70d6cc3f72451cd83b7276d35b2615">d_sw_mux</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a28918715849de2505bd480cccb5d6b4c">d_tx_freq</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a1b713d251419953e67467df19295c385">d_tx_modulator_shadow</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aad5f6f17a9fde484c67e7dbdd0491f74">d_udh</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4e5297f0010c8f39cfe4fff838b113a4">d_usb_data_rate</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a6d0fecbe64f35fef20293c27dc33a0b0">d_verbose</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a618be27f79f9ab769f33ead42c9283a7">dac_rate</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a25ef6153080bcd83637c87df6ea1d478">daughterboard_id</a>(int which_side) const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [inline, virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8eb1f58ca819437d7f43ad87574bd6da">db</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9e3dfe1821b5aa2438a014fd7ca579f4">db</a>(int which_side)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a386da4e76f7b2393563e48555c613a96">determine_tx_mux_value</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a24a7b471679b8e2485bfff5cce7adb96">determine_tx_mux_value</a>(const usrp_subdev_spec &ss_a, const usrp_subdev_spec &ss_b)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a2298762ed6e3f39c000a141a4964e181">disable_tx</a>()</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a244d4aa01bb6a054cd5bd0998ce2a09a">fpga_master_clock_freq</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#ac259e77beebe73376a45b6116ab845e1">has_rx_halfband</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a4192e505766a5920f8771bde1fd871ae">has_tx_halfband</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9d4d1ef184ad622c7f84a6f940614b9b">init_db</a>(usrp_basic_sptr u)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a2268e9e90e037cce86f9f83cce2a006d">interp_rate</a>() const </td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a61af504df443a9d846ecf909871f1481">is_valid</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ac156d958c028f4c30a18bda9f23ba8b9">make</a>(int which_board, unsigned int interp_rate, int nchan=1, int mux=-1, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#aee3b2b573a324ca3d8374566543f28ce">usrp_basic_tx::make</a>(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a2d21279d48272cf133db170b9f142218">MAX_CHAN</a></td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected, static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">MAX_REGS</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected, static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a18b5e48aee2ab110932d382b94e71268">mux</a>() const </td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#afc401f90409da171a5de0f91cf5749ef">nchannels</a>() const </td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a07b889dbe4fecd870f40ddf2401948c6">nddcs</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a9dec671bc0d7c50157083f46538844af">nducs</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#aa7764a14b980820287ebe3d50a303fbd">pga</a>(int which_amp) const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ac8f1b5ab8940fba58fe01d64727deb40">pga_db_per_step</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ac451445ef6cffdffb9e7817c3885f367">pga_max</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a7cae37094ad8d1a0095fc058649829d0">pga_min</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ac9e8934cb2136fd9c1f0bb2677991df0">probe_tx_slots</a>(bool verbose)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a237f04837e77f428551b6b66217f8d9b">read_aux_adc</a>(int which_side, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a1037a256b87c10e54e5650f80052cdc0">read_aux_adc</a>(int which_side, int which_adc)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aefe7a2f10626831304091babff21dc0d">read_eeprom</a>(int i2c_addr, int eeprom_offset, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a364d3e56a0749a90cc5de2ac378e6863">READ_FAILED</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab284caa2e15464f62aa80ad1f540ecc5">read_i2c</a>(int i2c_addr, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ad5b21bcc2798026f5a1555e9ca4c899f">read_io</a>(int which_side, int *value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a98999c00a4d121c09a234b23c63d8b42">read_io</a>(int which_side)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a7dd7dc05a7767f38ce25b407a705c2d5">restore_tx</a>(bool on)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a648de1479d7632b59bf2732f231ddbe0">selected_subdev</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a70a71308412a67eaf825c13399faa078">serial_number</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a97fc801cbafa85040a3d39be03d27a62">set_adc_buffer_bypass</a>(int which_adc, bool bypass)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad0e07c8d85aa220aaf150e27dd8b545f">set_adc_offset</a>(int which_adc, int offset)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ac19e5234b3139a369a9c7ad5844190ed">set_coarse_modulator</a>(int channel, coarse_mod_t cm)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected, virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab18f4a02c0efcac10f8e9406ca7a57a7">set_dac_offset</a>(int which_dac, int offset, int offset_pin)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af20cc324fca8d089226d5a6dfc3d3668">set_dc_offset_cl_enable</a>(int bits, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a825640d1de15253b5bae18762a0e403e">set_fpga_master_clock_freq</a>(long master_clock)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a51d29f5416c2db61e74e1938aa22af72">set_fpga_tx_sample_rate_divisor</a>(unsigned int div)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a7b092ae2811927291ffc3491e4461282">set_interp_rate</a>(unsigned int rate)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a2e432c316c8a91613b9603ebe664bfd1">set_mux</a>(int mux)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a5e9167c1f811c6446467ba2935cde618">set_nchannels</a>(int nchannels)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a5d950d5f8a8969e17525cee918d9bd06">set_pga</a>(int which_amp, double gain_in_db)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a13148a03a6d6df2be95679bc2bbea896">set_tx_enable</a>(bool on)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ae75deb35fef49d5e647b2141443d7106">set_tx_freq</a>(int channel, double freq)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a77535750946e7d8443a76941a9611cae">set_usb_data_rate</a>(int usb_data_rate)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ae200e6eb7dbbaf81a3c1353a401f97d3">set_verbose</a>(bool on)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#afaae41796f1468062d4ad237322baf9e">shutdown_daughterboards</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ae6f8039f30bf641b937877001127176f">start</a>()</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a5173292e6162fce54a875683f02cdd5c">stop</a>()</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a5c992590408fe90d4711e355ee12852f">tune</a>(int chan, db_base_sptr db, double target_freq, usrp_tune_result *result)</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ada7b24a807ade928dc5e57e823002f6d">tx_enable</a>() const </td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [inline, protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#aa527ce0117c6f6fb6e89f09efb4e381f">tx_freq</a>(int channel) const </td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a530c23ff633c630530ec491c368a755d">usb_data_rate</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac72f072eb9220e798019b60b3fe48af6">usrp_basic</a>(int which_board, libusb_device_handle *open_interface(libusb_device *dev), const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ab8bb942f1c956624553ac18b0a838bd6">usrp_basic_tx</a>(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a084f39cd160734d41e6c1cb8f6513dd6">usrp_standard_common</a>(usrp_basic *parent)</td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#ab3ebe65a0203867b6c71edcf2d4ffb88">usrp_standard_tx</a>(int which_board, unsigned int interp_rate, int nchan=1, int mux=-1, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#ad6486f2bff896af6109a338d7d954d50">wait_for_completion</a>()</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a0dd15899a23869336f455fa948b725af">write</a>(const void *buf, int len, bool *underrun)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a8cfd094ce093e5d46fcad5531ee20570">write_atr_mask</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad9b95b1ca0e2616c1b3808892fdda1b0">write_atr_rx_delay</a>(int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a01b222b0ba0a365db87ab74731325d5b">write_atr_rxval</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a70f4070830b0db3fd0c3addb97ce966e">write_atr_tx_delay</a>(int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#af4c224f2e92a07ded29fc6dedba8c2d7">write_atr_txval</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a2d3f6eda1859921bb7c0f26d2dd1163d">write_aux_dac</a>(int which_side, int which_dac, int value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a3900d37e951b83c938669f5fa0255866">write_eeprom</a>(int i2c_addr, int eeprom_offset, const std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#abd05aee7bbd18ef62bcc8dc18a11a960">write_hw_mux_reg</a>()</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a664e5aa3a3fb8a4c50b752906fcb79a0">write_i2c</a>(int i2c_addr, const std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a19a1a1db062ac7d3d4625c95770353ff">write_io</a>(int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a6076561547b3912ea535334e6e6d4c2f">write_refclk</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a01313a5f1c8e0eea1a1ff26388e25f78">~usrp_basic</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__tx.html#a1742407fda891ebf3eea8f297310e455">~usrp_basic_tx</a>()</td><td><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__tx.html#a440777cafe861f07ddeafa4d30327a1d">~usrp_standard_tx</a>()</td><td><a class="el" href="classusrp__standard__tx.html">usrp_standard_tx</a></td><td></td></tr>
</table></div>
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