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<h1>usrp_basic_tx Class Reference</h1><!-- doxytag: class="usrp_basic_tx" --><!-- doxytag: inherits="usrp_basic" -->
<p>class for accessing the transmit side of the USRP
<a href="#_details">More...</a></p>
<p><code>#include <<a class="el" href="usrp__basic_8h_source.html">usrp_basic.h</a>></code></p>
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Inheritance diagram for usrp_basic_tx:</div>
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<div class="center"><img src="classusrp__basic__tx__inherit__graph.png" border="0" usemap="#usrp__basic__tx_inherit__map" alt="Inheritance graph"/></div>
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<area shape="rect" id="node5" href="classusrp__standard__tx.html" title="The C++ interface the transmit side of the USRPThis is the recommended interface..." alt="" coords="5,160,128,189"/><area shape="rect" id="node2" href="classusrp__basic.html" title="abstract base class for usrp operations" alt="" coords="24,5,109,35"/></map>
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Collaboration diagram for usrp_basic_tx:</div>
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<area shape="rect" id="node2" href="classusrp__basic.html" title="abstract base class for usrp operations" alt="" coords="5,101,91,131"/><area shape="rect" id="node4" href="structusb__dev__handle.html" title="usb_dev_handle" alt="" coords="59,5,173,35"/><area shape="rect" id="node6" href="classfusb__devhandle.html" title="abstract usb device handle" alt="" coords="115,101,227,131"/><area shape="rect" id="node9" href="classfusb__ephandle.html" title="abstract usb end point handle" alt="" coords="251,101,357,131"/></map>
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<p><a href="classusrp__basic__tx-members.html">List of all members.</a></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Public Member Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a1742407fda891ebf3eea8f297310e455">~usrp_basic_tx</a> ()</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a51d29f5416c2db61e74e1938aa22af72">set_fpga_tx_sample_rate_divisor</a> (unsigned int div)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">tell the fpga the rate tx samples are going to the D/A's <a href="#a51d29f5416c2db61e74e1938aa22af72"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a0dd15899a23869336f455fa948b725af">write</a> (const void *buf, int len, bool *underrun)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write data to the A/D's via the FPGA. <a href="#a0dd15899a23869336f455fa948b725af"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ad6486f2bff896af6109a338d7d954d50">wait_for_completion</a> ()</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual long </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a4eefc136417ea3a75a296c1b6dbbd470">converter_rate</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">sampling rate of D/A converter <a href="#a4eefc136417ea3a75a296c1b6dbbd470"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">long </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a618be27f79f9ab769f33ead42c9283a7">dac_rate</a> () const </td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a25ef6153080bcd83637c87df6ea1d478">daughterboard_id</a> (int which_side) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return daughterboard ID for given side [0,1]. <a href="#a25ef6153080bcd83637c87df6ea1d478"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a5d950d5f8a8969e17525cee918d9bd06">set_pga</a> (int which_amp, double gain_in_db)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Set Programmable Gain Amplifier (PGA). <a href="#a5d950d5f8a8969e17525cee918d9bd06"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#aa7764a14b980820287ebe3d50a303fbd">pga</a> (int which_amp) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return programmable gain amplifier gain setting in dB. <a href="#aa7764a14b980820287ebe3d50a303fbd"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a7cae37094ad8d1a0095fc058649829d0">pga_min</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return minimum legal PGA gain in dB. <a href="#a7cae37094ad8d1a0095fc058649829d0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ac451445ef6cffdffb9e7817c3885f367">pga_max</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return maximum legal PGA gain in dB. <a href="#ac451445ef6cffdffb9e7817c3885f367"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ac8f1b5ab8940fba58fe01d64727deb40">pga_db_per_step</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return hardware step size of PGA (linear in dB). <a href="#ac8f1b5ab8940fba58fe01d64727deb40"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a0ecdfcb63c28d66b2f036156e33f20d8">_write_oe</a> (int which_side, int value, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write direction register (output enables) for pins that go to daughterboard. <a href="#a0ecdfcb63c28d66b2f036156e33f20d8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a19a1a1db062ac7d3d4625c95770353ff">write_io</a> (int which_side, int value, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard i/o pin value. <a href="#a19a1a1db062ac7d3d4625c95770353ff"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ad5b21bcc2798026f5a1555e9ca4c899f">read_io</a> (int which_side, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#ad5b21bcc2798026f5a1555e9ca4c899f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a98999c00a4d121c09a234b23c63d8b42">read_io</a> (int which_side)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#a98999c00a4d121c09a234b23c63d8b42"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a6076561547b3912ea535334e6e6d4c2f">write_refclk</a> (int which_side, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard refclk config register. <a href="#a6076561547b3912ea535334e6e6d4c2f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a8cfd094ce093e5d46fcad5531ee20570">write_atr_mask</a> (int which_side, int value)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#af4c224f2e92a07ded29fc6dedba8c2d7">write_atr_txval</a> (int which_side, int value)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a01b222b0ba0a365db87ab74731325d5b">write_atr_rxval</a> (int which_side, int value)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a2d3f6eda1859921bb7c0f26d2dd1163d">write_aux_dac</a> (int which_side, int which_dac, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write auxiliary digital to analog converter. <a href="#a2d3f6eda1859921bb7c0f26d2dd1163d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a237f04837e77f428551b6b66217f8d9b">read_aux_adc</a> (int which_side, int which_adc, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a237f04837e77f428551b6b66217f8d9b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a1037a256b87c10e54e5650f80052cdc0">read_aux_adc</a> (int which_side, int which_adc)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a1037a256b87c10e54e5650f80052cdc0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a3d88f6bddfb24f2ad375b65b935ac6e9">block_size</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">returns current fusb block size <a href="#a3d88f6bddfb24f2ad375b65b935ac6e9"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a3d16b0d8e96d5124b6392bc44014124d">start</a> ()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Start data transfers. Called in base class to derived class order. <a href="#a3d16b0d8e96d5124b6392bc44014124d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ab1c5851e72e29e86af914da5c7f62cf8">stop</a> ()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Stop data transfers. Called in base class to derived class order. <a href="#ab1c5851e72e29e86af914da5c7f62cf8"></a><br/></td></tr>
<tr><td colspan="2"><h2>Static Public Member Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#aee3b2b573a324ca3d8374566543f28ce">make</a> (int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">invokes constructor, returns instance or 0 if trouble <a href="#aee3b2b573a324ca3d8374566543f28ce"></a><br/></td></tr>
<tr><td colspan="2"><h2>Protected Member Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ab8bb942f1c956624553ac18b0a838bd6">usrp_basic_tx</a> (int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a13148a03a6d6df2be95679bc2bbea896">set_tx_enable</a> (bool on)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ada7b24a807ade928dc5e57e823002f6d">tx_enable</a> () const </td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a2298762ed6e3f39c000a141a4964e181">disable_tx</a> ()</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#a7dd7dc05a7767f38ce25b407a705c2d5">restore_tx</a> (bool on)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic__tx.html#ac9e8934cb2136fd9c1f0bb2677991df0">probe_tx_slots</a> (bool verbose)</td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>class for accessing the transmit side of the USRP </p>
<hr/><h2>Constructor & Destructor Documentation</h2>
<a class="anchor" id="ab8bb942f1c956624553ac18b0a838bd6"></a><!-- doxytag: member="usrp_basic_tx::usrp_basic_tx" ref="ab8bb942f1c956624553ac18b0a838bd6" args="(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")" -->
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<td class="memname">usrp_basic_tx::usrp_basic_tx </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_board</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>fusb_block_size</em> = <code>0</code>, </td>
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<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>fusb_nblocks</em> = <code>0</code>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>fpga_filename</em> = <code>""</code>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>firmware_filename</em> = <code>""</code></td><td> </td>
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<td></td>
<td>)</td>
<td></td><td></td><td><code> [protected]</code></td>
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<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_board</em> </td><td>Which USRP board on usb (not particularly useful; use 0) </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fusb_block_size</em> </td><td>fast usb xfer block size. Must be a multiple of 512. Use zero for a reasonable default. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fusb_nblocks</em> </td><td>number of fast usb URBs to allocate. Use zero for a reasonable default. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fpga_filename</em> </td><td>name of file that contains image to load into FPGA </td></tr>
<tr><td valign="top"></td><td valign="top"><em>firmware_filename</em> </td><td>name of file that contains image to load into FX2 </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00070">usrp_basic::d_ctx</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">usrp_basic::d_udh</a>, <a class="el" href="fusb__sysconfig__darwin_8cc_source.html#l00030">fusb_sysconfig::make_devhandle()</a>, <a class="el" href="classfusb__devhandle.html#a9783b6b0082f783dc7638ff557998ff2">fusb_devhandle::make_ephandle()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01393">probe_tx_slots()</a>, <a class="el" href="ad9862_8h_source.html#l00072">REG_TX_PWR_DN</a>, <a class="el" href="usrp__basic_8cc_source.html#l01308">set_fpga_tx_sample_rate_divisor()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01367">set_tx_enable()</a>, <a class="el" href="ad9862_8h_source.html#l00078">TX_PWR_DN_TX_ANALOG_BOTH</a>, <a class="el" href="ad9862_8h_source.html#l00075">TX_PWR_DN_TX_DIGITAL</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00877">usrp_9862_write()</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00926">usrp_9862_write_many_all()</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00533">usrp_set_fpga_tx_reset()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01501">write_atr_mask()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01513">write_atr_rxval()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01507">write_atr_txval()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01288">make()</a>.</p>
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<a class="anchor" id="a1742407fda891ebf3eea8f297310e455"></a><!-- doxytag: member="usrp_basic_tx::~usrp_basic_tx" ref="a1742407fda891ebf3eea8f297310e455" args="()" -->
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<td class="memname">usrp_basic_tx::~usrp_basic_tx </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<div class="memdoc">
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">usrp_basic::d_udh</a>, <a class="el" href="usrp__basic_8cc_source.html#l00168">usrp_basic::shutdown_daughterboards()</a>, <a class="el" href="classfusb__ephandle.html#a3cfe2cbb78870a6ce0ec8f696ebe45ab">fusb_ephandle::stop()</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00926">usrp_9862_write_many_all()</a>.</p>
</div>
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<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a0ecdfcb63c28d66b2f036156e33f20d8"></a><!-- doxytag: member="usrp_basic_tx::_write_oe" ref="a0ecdfcb63c28d66b2f036156e33f20d8" args="(int which_side, int value, int mask)" -->
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<td class="memname">bool usrp_basic_tx::_write_oe </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
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<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Write direction register (output enables) for pins that go to daughterboard. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which size </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg</td></tr>
</table>
</dd>
</dl>
<p>Each d'board has 16-bits of general purpose i/o. Setting the bit makes it an output from the FPGA to the d'board.</p>
<p>This register is initialized based on a value stored in the d'board EEPROM. In general, you shouldn't be using this routine without a very good reason. Using this method incorrectly will kill your USRP motherboard and/or daughterboard. </p>
<p>Implements <a class="el" href="classusrp__basic.html#ac540c04b719f1ce30426ecb2214107ef">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00639">usrp_basic::_common_write_oe()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>.</p>
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<a class="anchor" id="a3d88f6bddfb24f2ad375b65b935ac6e9"></a><!-- doxytag: member="usrp_basic_tx::block_size" ref="a3d88f6bddfb24f2ad375b65b935ac6e9" args="() const " -->
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<td class="memname">int usrp_basic_tx::block_size </td>
<td>(</td>
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<td> ) </td>
<td> const<code> [virtual]</code></td>
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<p>returns current fusb block size </p>
<p>Implements <a class="el" href="classusrp__basic.html#a1f769dc9ea28d701fa2f7da2be82325d">usrp_basic</a>.</p>
<p>References <a class="el" href="fusb_8h_source.html#l00106">fusb_ephandle::block_size()</a>.</p>
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<a class="anchor" id="a4eefc136417ea3a75a296c1b6dbbd470"></a><!-- doxytag: member="usrp_basic_tx::converter_rate" ref="a4eefc136417ea3a75a296c1b6dbbd470" args="() const " -->
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<td class="memname">virtual long usrp_basic_tx::converter_rate </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline, virtual]</code></td>
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<p>sampling rate of D/A converter </p>
<p>Implements <a class="el" href="classusrp__basic.html#a551a0912d265427e595ba826858cf3d0">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00183">usrp_basic::fpga_master_clock_freq()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8h_source.html#l00964">dac_rate()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l01171">usrp_standard_tx::tune()</a>.</p>
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<a class="anchor" id="a618be27f79f9ab769f33ead42c9283a7"></a><!-- doxytag: member="usrp_basic_tx::dac_rate" ref="a618be27f79f9ab769f33ead42c9283a7" args="() const " -->
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<td class="memname">long usrp_basic_tx::dac_rate </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline]</code></td>
</tr>
</table>
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<p>References <a class="el" href="usrp__basic_8h_source.html#l00963">converter_rate()</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00897">usrp_standard_tx::set_interp_rate()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l01018">usrp_standard_tx::set_tx_freq()</a>.</p>
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<a class="anchor" id="a25ef6153080bcd83637c87df6ea1d478"></a><!-- doxytag: member="usrp_basic_tx::daughterboard_id" ref="a25ef6153080bcd83637c87df6ea1d478" args="(int which_side) const " -->
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<td class="memname">int usrp_basic_tx::daughterboard_id </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td>
<td> ) </td>
<td> const<code> [inline, virtual]</code></td>
</tr>
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<p>Return daughterboard ID for given side [0,1]. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which daughterboard</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>daughterboard id >= 0 if successful </dd>
<dd>
-1 if no daugherboard </dd>
<dd>
-2 if invalid EEPROM on daughterboard </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#a6d639e50633c165b23e0c4770b26bec2">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00079">usrp_basic::d_dbid</a>.</p>
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<a class="anchor" id="a2298762ed6e3f39c000a141a4964e181"></a><!-- doxytag: member="usrp_basic_tx::disable_tx" ref="a2298762ed6e3f39c000a141a4964e181" args="()" -->
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<td class="memname">bool usrp_basic_tx::disable_tx </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td><code> [protected]</code></td>
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<p>References <a class="el" href="usrp__basic_8cc_source.html#l01367">set_tx_enable()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00908">tx_enable()</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00897">usrp_standard_tx::set_interp_rate()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00942">usrp_standard_tx::write_hw_mux_reg()</a>.</p>
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<a class="anchor" id="aee3b2b573a324ca3d8374566543f28ce"></a><!-- doxytag: member="usrp_basic_tx::make" ref="aee3b2b573a324ca3d8374566543f28ce" args="(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")" -->
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<td class="memname"><a class="el" href="classusrp__basic__tx.html">usrp_basic_tx</a> * usrp_basic_tx::make </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_board</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>fusb_block_size</em> = <code>0</code>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>fusb_nblocks</em> = <code>0</code>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>fpga_filename</em> = <code>""</code>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>firmware_filename</em> = <code>""</code></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [static]</code></td>
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<p>invokes constructor, returns instance or 0 if trouble </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_board</em> </td><td>Which USRP board on usb (not particularly useful; use 0) </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fusb_block_size</em> </td><td>fast usb xfer block size. Must be a multiple of 512. Use zero for a reasonable default. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fusb_nblocks</em> </td><td>number of fast usb URBs to allocate. Use zero for a reasonable default. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>fpga_filename</em> </td><td>name of file that contains image to load into FPGA </td></tr>
<tr><td valign="top"></td><td valign="top"><em>firmware_filename</em> </td><td>name of file that contains image to load into FX2 </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="aa7764a14b980820287ebe3d50a303fbd"></a><!-- doxytag: member="usrp_basic_tx::pga" ref="aa7764a14b980820287ebe3d50a303fbd" args="(int which_amp) const " -->
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<td class="memname">double usrp_basic_tx::pga </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em></td>
<td> ) </td>
<td> const<code> [virtual]</code></td>
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<p>Return programmable gain amplifier gain setting in dB. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
</table>
</dd>
</dl>
<p>Implements <a class="el" href="classusrp__basic.html#a731389d216c7232020041f7cecd3d581">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00585">usrp_basic::common_pga()</a>.</p>
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<a class="anchor" id="ac8f1b5ab8940fba58fe01d64727deb40"></a><!-- doxytag: member="usrp_basic_tx::pga_db_per_step" ref="ac8f1b5ab8940fba58fe01d64727deb40" args="() const " -->
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<td class="memname">double usrp_basic_tx::pga_db_per_step </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [virtual]</code></td>
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<p>Return hardware step size of PGA (linear in dB). </p>
<p>Implements <a class="el" href="classusrp__basic.html#ae67abb570f10f1216c001f2409fe3331">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00630">usrp_basic::common_pga_db_per_step()</a>.</p>
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<a class="anchor" id="ac451445ef6cffdffb9e7817c3885f367"></a><!-- doxytag: member="usrp_basic_tx::pga_max" ref="ac451445ef6cffdffb9e7817c3885f367" args="() const " -->
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<td class="memname">double usrp_basic_tx::pga_max </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [virtual]</code></td>
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<p>Return maximum legal PGA gain in dB. </p>
<p>Implements <a class="el" href="classusrp__basic.html#ae6a0027c59862dcc2d4da73d50b6a598">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00621">usrp_basic::common_pga_max()</a>.</p>
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<a class="anchor" id="a7cae37094ad8d1a0095fc058649829d0"></a><!-- doxytag: member="usrp_basic_tx::pga_min" ref="a7cae37094ad8d1a0095fc058649829d0" args="() const " -->
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<td class="memname">double usrp_basic_tx::pga_min </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [virtual]</code></td>
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<p>Return minimum legal PGA gain in dB. </p>
<p>Implements <a class="el" href="classusrp__basic.html#afcab635a411c57f16820e44a83bfe259">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00612">usrp_basic::common_pga_min()</a>.</p>
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<a class="anchor" id="ac9e8934cb2136fd9c1f0bb2677991df0"></a><!-- doxytag: member="usrp_basic_tx::probe_tx_slots" ref="ac9e8934cb2136fd9c1f0bb2677991df0" args="(bool verbose)" -->
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<td class="memname">void usrp_basic_tx::probe_tx_slots </td>
<td>(</td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>verbose</em></td>
<td> ) </td>
<td><code> [protected]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">usrp_basic::_write_fpga_reg()</a>, <a class="el" href="usrp__basic_8h_source.html#l00079">usrp_basic::d_dbid</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">usrp_basic::d_udh</a>, <a class="el" href="usrp__prims_8h_source.html#l00280">usrp_dboard_eeprom::id</a>, <a class="el" href="usrp__prims_8h_source.html#l00281">usrp_dboard_eeprom::oe</a>, <a class="el" href="usrp__prims_8h_source.html#l00277">UDBE_BAD_SLOT</a>, <a class="el" href="usrp__prims_8h_source.html#l00277">UDBE_INVALID_EEPROM</a>, <a class="el" href="usrp__prims_8h_source.html#l00277">UDBE_NO_EEPROM</a>, <a class="el" href="usrp__prims_8h_source.html#l00277">UDBE_OK</a>, <a class="el" href="usrp__dbid_8cc_source.html#l00093">usrp_dbid_to_string()</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l01181">usrp_read_dboard_eeprom()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a1037a256b87c10e54e5650f80052cdc0"></a><!-- doxytag: member="usrp_basic_tx::read_aux_adc" ref="a1037a256b87c10e54e5650f80052cdc0" args="(int which_side, int which_adc)" -->
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<td class="memname">int usrp_basic_tx::read_aux_adc </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
</tr>
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<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value in the range [0,4095] if successful, else READ_FAILED. </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#ab8b3158fe7448c951ad78bb54a06f5c5">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00736">usrp_basic::common_read_aux_adc()</a>.</p>
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<a class="anchor" id="a237f04837e77f428551b6b66217f8d9b"></a><!-- doxytag: member="usrp_basic_tx::read_aux_adc" ref="a237f04837e77f428551b6b66217f8d9b" args="(int which_side, int which_adc, int *value)" -->
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<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
</tr>
</table>
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<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>return 12-bit value [0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#a7e90fb51366e9d6a8f2c844dbca2798a">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00736">usrp_basic::common_read_aux_adc()</a>.</p>
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<a class="anchor" id="a98999c00a4d121c09a234b23c63d8b42"></a><!-- doxytag: member="usrp_basic_tx::read_io" ref="a98999c00a4d121c09a234b23c63d8b42" args="(int which_side)" -->
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<td class="memname">int usrp_basic_tx::read_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td>
<td> ) </td>
<td><code> [virtual]</code></td>
</tr>
</table>
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<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>register value if successful, else READ_FAILED </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#a166feedb83f6425d3bbbbf65f29bf42c">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00659">usrp_basic::common_read_io()</a>.</p>
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<a class="anchor" id="ad5b21bcc2798026f5a1555e9ca4c899f"></a><!-- doxytag: member="usrp_basic_tx::read_io" ref="ad5b21bcc2798026f5a1555e9ca4c899f" args="(int which_side, int *value)" -->
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<td class="memname">bool usrp_basic_tx::read_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>output </td></tr>
</table>
</dd>
</dl>
<p>Implements <a class="el" href="classusrp__basic.html#ad443caee9815e7c69a8b39a29cf8846a">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00659">usrp_basic::common_read_io()</a>.</p>
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<a class="anchor" id="a7dd7dc05a7767f38ce25b407a705c2d5"></a><!-- doxytag: member="usrp_basic_tx::restore_tx" ref="a7dd7dc05a7767f38ce25b407a705c2d5" args="(bool on)" -->
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<td class="memname">void usrp_basic_tx::restore_tx </td>
<td>(</td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>on</em></td>
<td> ) </td>
<td><code> [protected]</code></td>
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<p>References <a class="el" href="usrp__basic_8cc_source.html#l01367">set_tx_enable()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00908">tx_enable()</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00897">usrp_standard_tx::set_interp_rate()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00942">usrp_standard_tx::write_hw_mux_reg()</a>.</p>
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<a class="anchor" id="a51d29f5416c2db61e74e1938aa22af72"></a><!-- doxytag: member="usrp_basic_tx::set_fpga_tx_sample_rate_divisor" ref="a51d29f5416c2db61e74e1938aa22af72" args="(unsigned int div)" -->
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<td class="memname">bool usrp_basic_tx::set_fpga_tx_sample_rate_divisor </td>
<td>(</td>
<td class="paramtype">unsigned int </td>
<td class="paramname"> <em>div</em></td>
<td> ) </td>
<td></td>
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<p>tell the fpga the rate tx samples are going to the D/A's </p>
<p>div = fpga_master_clock_freq () * 2</p>
<p>sample_rate is determined by a myriad of registers in the 9862. That's why you have to tell us, so we can tell the fpga. </p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">usrp_basic::_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a5d950d5f8a8969e17525cee918d9bd06"></a><!-- doxytag: member="usrp_basic_tx::set_pga" ref="a5d950d5f8a8969e17525cee918d9bd06" args="(int which_amp, double gain_in_db)" -->
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<td class="memname">bool usrp_basic_tx::set_pga </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">double </td>
<td class="paramname"> <em>gain_in_db</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Set Programmable Gain Amplifier (PGA). </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>gain_in_db</em> </td><td>gain value (linear in dB)</td></tr>
</table>
</dd>
</dl>
<p>gain is rounded to closest setting supported by hardware.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff sucessful.</dd></dl>
<dl class="see"><dt><b>See also:</b></dt><dd><a class="el" href="classusrp__basic__tx.html#a7cae37094ad8d1a0095fc058649829d0" title="Return minimum legal PGA gain in dB.">pga_min()</a>, <a class="el" href="classusrp__basic__tx.html#ac451445ef6cffdffb9e7817c3885f367" title="Return maximum legal PGA gain in dB.">pga_max()</a>, <a class="el" href="classusrp__basic__tx.html#ac8f1b5ab8940fba58fe01d64727deb40" title="Return hardware step size of PGA (linear in dB).">pga_db_per_step()</a> </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#afdcf0497f2554589b36a57806e239a07">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00557">usrp_basic::common_set_pga()</a>.</p>
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<a class="anchor" id="a13148a03a6d6df2be95679bc2bbea896"></a><!-- doxytag: member="usrp_basic_tx::set_tx_enable" ref="a13148a03a6d6df2be95679bc2bbea896" args="(bool on)" -->
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<td class="memname">bool usrp_basic_tx::set_tx_enable </td>
<td>(</td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>on</em></td>
<td> ) </td>
<td><code> [protected]</code></td>
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<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">usrp_basic::d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00521">usrp_set_fpga_tx_enable()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01376">disable_tx()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01386">restore_tx()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01251">start()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01270">stop()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a3d16b0d8e96d5124b6392bc44014124d"></a><!-- doxytag: member="usrp_basic_tx::start" ref="a3d16b0d8e96d5124b6392bc44014124d" args="()" -->
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<td class="memname">bool usrp_basic_tx::start </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<p>Start data transfers. Called in base class to derived class order. </p>
<p>Reimplemented from <a class="el" href="classusrp__basic.html#a4291ecf3cc0870baaa12644143182db4">usrp_basic</a>.</p>
<p>Reimplemented in <a class="el" href="classusrp__standard__tx.html#ae6f8039f30bf641b937877001127176f">usrp_standard_tx</a>.</p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l01367">set_tx_enable()</a>, <a class="el" href="classfusb__ephandle.html#aac0498804e009ab78c47f2265f34a054">fusb_ephandle::start()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00217">usrp_basic::start()</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00854">usrp_standard_tx::start()</a>.</p>
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<a class="anchor" id="ab1c5851e72e29e86af914da5c7f62cf8"></a><!-- doxytag: member="usrp_basic_tx::stop" ref="ab1c5851e72e29e86af914da5c7f62cf8" args="()" -->
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<td class="memname">bool usrp_basic_tx::stop </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<p>Stop data transfers. Called in base class to derived class order. </p>
<p>Reimplemented from <a class="el" href="classusrp__basic.html#a69292bbc3b47b5ca85d4c0404dc4a58a">usrp_basic</a>.</p>
<p>Reimplemented in <a class="el" href="classusrp__standard__tx.html#a5173292e6162fce54a875683f02cdd5c">usrp_standard_tx</a>.</p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l01367">set_tx_enable()</a>, and <a class="el" href="classfusb__ephandle.html#a3cfe2cbb78870a6ce0ec8f696ebe45ab">fusb_ephandle::stop()</a>.</p>
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<a class="anchor" id="ada7b24a807ade928dc5e57e823002f6d"></a><!-- doxytag: member="usrp_basic_tx::tx_enable" ref="ada7b24a807ade928dc5e57e823002f6d" args="() const " -->
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<td class="memname">bool usrp_basic_tx::tx_enable </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline, protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01376">disable_tx()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01386">restore_tx()</a>.</p>
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<a class="anchor" id="ad6486f2bff896af6109a338d7d954d50"></a><!-- doxytag: member="usrp_basic_tx::wait_for_completion" ref="ad6486f2bff896af6109a338d7d954d50" args="()" -->
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<td class="memname">void usrp_basic_tx::wait_for_completion </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<p>References <a class="el" href="classfusb__ephandle.html#a1e1a2c7173a14aea99686fad7c0e061c">fusb_ephandle::wait_for_completion()</a>.</p>
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<a class="anchor" id="a0dd15899a23869336f455fa948b725af"></a><!-- doxytag: member="usrp_basic_tx::write" ref="a0dd15899a23869336f455fa948b725af" args="(const void *buf, int len, bool *underrun)" -->
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<td class="memname">int usrp_basic_tx::write </td>
<td>(</td>
<td class="paramtype">const void * </td>
<td class="paramname"> <em>buf</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>len</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool * </td>
<td class="paramname"> <em>underrun</em></td><td> </td>
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<td></td>
<td>)</td>
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<p>Write data to the A/D's via the FPGA. </p>
<p><code>len</code> must be a multiple of 512 bytes. </p>
<dl class="return"><dt><b>Returns:</b></dt><dd>number of bytes written or -1 on error.</dd></dl>
<p>if <code>underrun</code> is non-NULL, it will be set to true iff a transmit underrun condition is detected. </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00072">usrp_basic::d_bytes_per_poll</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">usrp_basic::d_udh</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00818">usrp_check_tx_underrun()</a>, and <a class="el" href="classfusb__ephandle.html#ab2a965c0f5fea6632bc08ea59c8c8fe1">fusb_ephandle::write()</a>.</p>
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<a class="anchor" id="a8cfd094ce093e5d46fcad5531ee20570"></a><!-- doxytag: member="usrp_basic_tx::write_atr_mask" ref="a8cfd094ce093e5d46fcad5531ee20570" args="(int which_side, int value)" -->
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<td class="memname">bool usrp_basic_tx::write_atr_mask </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Implements <a class="el" href="classusrp__basic.html#a49074783b3757b6af17ddf8e8f56be6c">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00700">usrp_basic::common_write_atr_mask()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a01b222b0ba0a365db87ab74731325d5b"></a><!-- doxytag: member="usrp_basic_tx::write_atr_rxval" ref="a01b222b0ba0a365db87ab74731325d5b" args="(int which_side, int value)" -->
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<td class="memname">bool usrp_basic_tx::write_atr_rxval </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Implements <a class="el" href="classusrp__basic.html#ae5466590dd7ec5646fefbb82d92ad899">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00720">usrp_basic::common_write_atr_rxval()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="af4c224f2e92a07ded29fc6dedba8c2d7"></a><!-- doxytag: member="usrp_basic_tx::write_atr_txval" ref="af4c224f2e92a07ded29fc6dedba8c2d7" args="(int which_side, int value)" -->
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<td class="memname">bool usrp_basic_tx::write_atr_txval </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Implements <a class="el" href="classusrp__basic.html#a504bf45d241c56ddf00ee07fc946207e">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00710">usrp_basic::common_write_atr_txval()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a2d3f6eda1859921bb7c0f26d2dd1163d"></a><!-- doxytag: member="usrp_basic_tx::write_aux_dac" ref="a2d3f6eda1859921bb7c0f26d2dd1163d" args="(int which_side, int which_dac, int value)" -->
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<td class="memname">bool usrp_basic_tx::write_aux_dac </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_dac</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
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<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Write auxiliary digital to analog converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_dac</em> </td><td>[2,3] TX slots must use only 2 and 3. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>[0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>Implements <a class="el" href="classusrp__basic.html#a332790fa84b6b64f82de8983b45b611a">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00730">usrp_basic::common_write_aux_dac()</a>.</p>
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<a class="anchor" id="a19a1a1db062ac7d3d4625c95770353ff"></a><!-- doxytag: member="usrp_basic_tx::write_io" ref="a19a1a1db062ac7d3d4625c95770353ff" args="(int which_side, int value, int mask)" -->
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<td class="memname">bool usrp_basic_tx::write_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
</tr>
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<p>Write daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg </td></tr>
</table>
</dd>
</dl>
<p>Implements <a class="el" href="classusrp__basic.html#a75aca6cca672ac2deedf14fb2c04ab0e">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00649">usrp_basic::common_write_io()</a>.</p>
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<a class="anchor" id="a6076561547b3912ea535334e6e6d4c2f"></a><!-- doxytag: member="usrp_basic_tx::write_refclk" ref="a6076561547b3912ea535334e6e6d4c2f" args="(int which_side, int value)" -->
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<td class="memname">bool usrp_basic_tx::write_refclk </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td><code> [virtual]</code></td>
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<p>Write daughterboard refclk config register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register, see below</td></tr>
</table>
</dd>
</dl>
<pre>
Control whether a reference clock is sent to the daughterboards,
and what frequency. The refclk is sent on d'board i/o pin 0.</pre><pre> 3 2 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------------------------------------------+-+------------+
| Reserved (Must be zero) |E| DIVISOR |
+-----------------------------------------------+-+------------+</pre><pre> Bit 7 -- 1 turns on refclk, 0 allows IO use
Bits 6:0 Divider value
</pre>
<p>Implements <a class="el" href="classusrp__basic.html#a80a4f8800742b6b06ec6f1908a448fc8">usrp_basic</a>.</p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00690">usrp_basic::common_write_refclk()</a>.</p>
</div>
</div>
<hr/>The documentation for this class was generated from the following files:<ul>
<li><a class="el" href="usrp__basic_8h_source.html">usrp_basic.h</a></li>
<li><a class="el" href="usrp__basic_8cc.html">usrp_basic.cc</a></li>
</ul>
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<hr class="footer"/><address style="text-align: right;"><small>Generated on Wed Dec 29 19:44:44 2010 for Universal Software Radio Peripheral by
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.3 </small></address>
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distrib
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Mandriva
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2010.2
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i586
>
media
>
contrib-backports
>
by-pkgid
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e1990170655e25252b23301d6cebc16d
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files
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654
