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<h1>usrp_basic Class Reference</h1><!-- doxytag: class="usrp_basic" -->
<p>abstract base class for usrp operations
<a href="#_details">More...</a></p>
<p><code>#include <<a class="el" href="usrp__basic_8h_source.html">usrp_basic.h</a>></code></p>
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Inheritance diagram for usrp_basic:</div>
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<area shape="rect" id="node3" href="classusrp__basic__rx.html" title="class for accessing the receive side of the USRP" alt="" coords="21,83,123,112"/><area shape="rect" id="node7" href="classusrp__basic__tx.html" title="class for accessing the transmit side of the USRP" alt="" coords="157,83,259,112"/><area shape="rect" id="node5" href="classusrp__standard__rx.html" title="The C++ interface the receive side of the USRPThis is the recommended interface to..." alt="" coords="5,160,128,189"/><area shape="rect" id="node9" href="classusrp__standard__tx.html" title="The C++ interface the transmit side of the USRPThis is the recommended interface..." alt="" coords="152,160,275,189"/></map>
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Collaboration diagram for usrp_basic:</div>
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<p><a href="classusrp__basic-members.html">List of all members.</a></p>
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<tr><td colspan="2"><h2>Public Member Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a01313a5f1c8e0eea1a1ff26388e25f78">~usrp_basic</a> ()</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::vector< std::vector<br class="typebreak"/>
< <a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> > > </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a8eb1f58ca819437d7f43ad87574bd6da">db</a> () const </td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::vector< <a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a9e3dfe1821b5aa2438a014fd7ca579f4">db</a> (int which_side)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a61af504df443a9d846ecf909871f1481">is_valid</a> (const <a class="el" href="structusrp__subdev__spec.html">usrp_subdev_spec</a> &ss)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">is the subdev_spec valid? <a href="#a61af504df443a9d846ecf909871f1481"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a648de1479d7632b59bf2732f231ddbe0">selected_subdev</a> (const <a class="el" href="structusrp__subdev__spec.html">usrp_subdev_spec</a> &ss)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">given a subdev_spec, return the corresponding daughterboard object. <a href="#a648de1479d7632b59bf2732f231ddbe0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">long </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a244d4aa01bb6a054cd5bd0998ce2a09a">fpga_master_clock_freq</a> () const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">return frequency of master oscillator on USRP <a href="#a244d4aa01bb6a054cd5bd0998ce2a09a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a825640d1de15253b5bae18762a0e403e">set_fpga_master_clock_freq</a> (long master_clock)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a530c23ff633c630530ec491c368a755d">usb_data_rate</a> () const </td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ae200e6eb7dbbaf81a3c1353a401f97d3">set_verbose</a> (bool on)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a3900d37e951b83c938669f5fa0255866">write_eeprom</a> (int i2c_addr, int eeprom_offset, const std::string buf)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write EEPROM on motherboard or any daughterboard. <a href="#a3900d37e951b83c938669f5fa0255866"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#aefe7a2f10626831304091babff21dc0d">read_eeprom</a> (int i2c_addr, int eeprom_offset, int len)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read EEPROM on motherboard or any daughterboard. <a href="#aefe7a2f10626831304091babff21dc0d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a664e5aa3a3fb8a4c50b752906fcb79a0">write_i2c</a> (int i2c_addr, const std::string buf)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write to I2C peripheral. <a href="#a664e5aa3a3fb8a4c50b752906fcb79a0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ab284caa2e15464f62aa80ad1f540ecc5">read_i2c</a> (int i2c_addr, int len)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read from I2C peripheral. <a href="#ab284caa2e15464f62aa80ad1f540ecc5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ad0e07c8d85aa220aaf150e27dd8b545f">set_adc_offset</a> (int which_adc, int offset)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Set ADC offset correction. <a href="#ad0e07c8d85aa220aaf150e27dd8b545f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ab18f4a02c0efcac10f8e9406ca7a57a7">set_dac_offset</a> (int which_dac, int offset, int offset_pin)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Set DAC offset correction. <a href="#ab18f4a02c0efcac10f8e9406ca7a57a7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a97fc801cbafa85040a3d39be03d27a62">set_adc_buffer_bypass</a> (int which_adc, bool bypass)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Control ADC input buffer. <a href="#a97fc801cbafa85040a3d39be03d27a62"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#af20cc324fca8d089226d5a6dfc3d3668">set_dc_offset_cl_enable</a> (int bits, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable automatic DC offset removal control loop in FPGA. <a href="#af20cc324fca8d089226d5a6dfc3d3668"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a70a71308412a67eaf825c13399faa078">serial_number</a> ()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">return the usrp's serial number. <a href="#a70a71308412a67eaf825c13399faa078"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a6d639e50633c165b23e0c4770b26bec2">daughterboard_id</a> (int which_side) const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return daughterboard ID for given side [0,1]. <a href="#a6d639e50633c165b23e0c4770b26bec2"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a70f4070830b0db3fd0c3addb97ce966e">write_atr_tx_delay</a> (int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Clock ticks to delay rising of T/R signal. <a href="#a70f4070830b0db3fd0c3addb97ce966e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ad9b95b1ca0e2616c1b3808892fdda1b0">write_atr_rx_delay</a> (int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Clock ticks to delay falling edge of T/R signal. <a href="#ad9b95b1ca0e2616c1b3808892fdda1b0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a52f96a90c91ed6e74bfc6a91691a7fa2">common_set_pga</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_amp, double gain_in_db)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Set Programmable Gain Amplifier(PGA). <a href="#a52f96a90c91ed6e74bfc6a91691a7fa2"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ac25d56e74572309a87397f0fce1a102b">common_pga</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_amp) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return programmable gain amplifier gain setting in dB. <a href="#ac25d56e74572309a87397f0fce1a102b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a95453e5bb4d0ed4c05b1ea64c880170a">common_pga_min</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return minimum legal PGA gain in dB. <a href="#a95453e5bb4d0ed4c05b1ea64c880170a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a7dd5c384b9d2cd4e412939c3b7b7ac79">common_pga_max</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return maximum legal PGA gain in dB. <a href="#a7dd5c384b9d2cd4e412939c3b7b7ac79"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a06cfd0e5675618f773c5466bd235a369">common_pga_db_per_step</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return hardware step size of PGA(linear in dB). <a href="#a06cfd0e5675618f773c5466bd235a369"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a09ce78134eea035e42464123356096e4">_common_write_oe</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write direction register(output enables) for pins that go to daughterboard. <a href="#a09ce78134eea035e42464123356096e4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#acf3120592af4df79d38d253c98c633ae">common_write_io</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard i/o pin value. <a href="#acf3120592af4df79d38d253c98c633ae"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#af7e33b5762cd9c80a714806fa6fa2244">common_read_io</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#af7e33b5762cd9c80a714806fa6fa2244"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a217f6865ef04d1111c2c1d3e7b4260f5">common_read_io</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#a217f6865ef04d1111c2c1d3e7b4260f5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ad673bc49b311e29ab01727c5933ea028">common_write_refclk</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard refclk config register. <a href="#ad673bc49b311e29ab01727c5933ea028"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a0997e93568c71e5432c2445b1ebcc991">common_write_atr_mask</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Automatic Transmit/Receive switching. <a href="#a0997e93568c71e5432c2445b1ebcc991"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a26e38a0f9f98390b712709812e3387af">common_write_atr_txval</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a89eda6a96bc7f4d2d634da793eccbc20">common_write_atr_rxval</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int value)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ac7354a9c4f7e961cb1b541c970a8d009">common_write_aux_dac</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int which_dac, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write auxiliary digital to analog converter. <a href="#ac7354a9c4f7e961cb1b541c970a8d009"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a37bd03473a98cf3776f1988914c1a5ce">common_read_aux_adc</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int which_adc, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a37bd03473a98cf3776f1988914c1a5ce"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ab84d66e92dc16fdc104fae9341f1e64f">common_read_aux_adc</a> (<a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> txrx, int which_side, int which_adc)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#ab84d66e92dc16fdc104fae9341f1e64f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#afdcf0497f2554589b36a57806e239a07">set_pga</a> (int which_amp, double gain_in_db)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Set Programmable Gain Amplifier (PGA). <a href="#afdcf0497f2554589b36a57806e239a07"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a731389d216c7232020041f7cecd3d581">pga</a> (int which_amp) const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return programmable gain amplifier gain setting in dB. <a href="#a731389d216c7232020041f7cecd3d581"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#afcab635a411c57f16820e44a83bfe259">pga_min</a> () const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return minimum legal PGA gain in dB. <a href="#afcab635a411c57f16820e44a83bfe259"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ae6a0027c59862dcc2d4da73d50b6a598">pga_max</a> () const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return maximum legal PGA gain in dB. <a href="#ae6a0027c59862dcc2d4da73d50b6a598"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual double </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ae67abb570f10f1216c001f2409fe3331">pga_db_per_step</a> () const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return hardware step size of PGA (linear in dB). <a href="#ae67abb570f10f1216c001f2409fe3331"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ac540c04b719f1ce30426ecb2214107ef">_write_oe</a> (int which_side, int value, int mask)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write direction register (output enables) for pins that go to daughterboard. <a href="#ac540c04b719f1ce30426ecb2214107ef"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a75aca6cca672ac2deedf14fb2c04ab0e">write_io</a> (int which_side, int value, int mask)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard i/o pin value. <a href="#a75aca6cca672ac2deedf14fb2c04ab0e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ad443caee9815e7c69a8b39a29cf8846a">read_io</a> (int which_side, int *value)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#ad443caee9815e7c69a8b39a29cf8846a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a166feedb83f6425d3bbbbf65f29bf42c">read_io</a> (int which_side)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read daughterboard i/o pin value. <a href="#a166feedb83f6425d3bbbbf65f29bf42c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a80a4f8800742b6b06ec6f1908a448fc8">write_refclk</a> (int which_side, int value)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write daughterboard refclk config register. <a href="#a80a4f8800742b6b06ec6f1908a448fc8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a49074783b3757b6af17ddf8e8f56be6c">write_atr_mask</a> (int which_side, int value)=0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a504bf45d241c56ddf00ee07fc946207e">write_atr_txval</a> (int which_side, int value)=0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ae5466590dd7ec5646fefbb82d92ad899">write_atr_rxval</a> (int which_side, int value)=0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a332790fa84b6b64f82de8983b45b611a">write_aux_dac</a> (int which_side, int which_dac, int value)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write auxiliary digital to analog converter. <a href="#a332790fa84b6b64f82de8983b45b611a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a7e90fb51366e9d6a8f2c844dbca2798a">read_aux_adc</a> (int which_side, int which_adc, int *value)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a7e90fb51366e9d6a8f2c844dbca2798a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ab8b3158fe7448c951ad78bb54a06f5c5">read_aux_adc</a> (int which_side, int which_adc)=0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#ab8b3158fe7448c951ad78bb54a06f5c5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a1f769dc9ea28d701fa2f7da2be82325d">block_size</a> () const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">returns current fusb block size <a href="#a1f769dc9ea28d701fa2f7da2be82325d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">virtual long </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a551a0912d265427e595ba826858cf3d0">converter_rate</a> () const =0</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">returns A/D or D/A converter rate in Hz <a href="#a551a0912d265427e595ba826858cf3d0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a4585f9c7df7084a6acb29bd6d7950892">_set_led</a> (int which_led, bool on)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ac5bdb9be69f27eb3a0530cba9536d0f4">_write_fpga_reg</a> (int regno, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write FPGA register. <a href="#ac5bdb9be69f27eb3a0530cba9536d0f4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a4fa26bd8164bd5782adf7fbe00b3d411">_read_fpga_reg</a> (int regno, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read FPGA register. <a href="#a4fa26bd8164bd5782adf7fbe00b3d411"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#abf1f167a1c96dd0ed4589afc6c9fad6c">_read_fpga_reg</a> (int regno)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read FPGA register. <a href="#abf1f167a1c96dd0ed4589afc6c9fad6c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a0c200dc2d39d68d7a77e92859c5228a0">_write_fpga_reg_masked</a> (int regno, int value, int mask)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write FPGA register with mask. <a href="#a0c200dc2d39d68d7a77e92859c5228a0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a8a25444c83f59f7517d0ff687d2ff053">_write_9862</a> (int which_codec, int regno, unsigned char value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write AD9862 register. <a href="#a8a25444c83f59f7517d0ff687d2ff053"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a3814dc28edce07e3b5cb48bb3ebdf244">_read_9862</a> (int which_codec, int regno, unsigned char *value) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read AD9862 register. <a href="#a3814dc28edce07e3b5cb48bb3ebdf244"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ad28278c9ff7a33b3a151c561ab037b9f">_read_9862</a> (int which_codec, int regno) const </td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read AD9862 register. <a href="#ad28278c9ff7a33b3a151c561ab037b9f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#aaf100fafc406ef75faafcf3e38df7849">_write_spi</a> (int optional_header, int enables, int format, std::string buf)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write data to SPI bus peripheral. <a href="#aaf100fafc406ef75faafcf3e38df7849"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a9b54622fec87c2ed9c7808078931371f">_read_spi</a> (int optional_header, int enables, int format, int len)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a4291ecf3cc0870baaa12644143182db4">start</a> ()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Start data transfers. Called in base class to derived class order. <a href="#a4291ecf3cc0870baaa12644143182db4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a69292bbc3b47b5ca85d4c0404dc4a58a">stop</a> ()</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Stop data transfers. Called in base class to derived class order. <a href="#a69292bbc3b47b5ca85d4c0404dc4a58a"></a><br/></td></tr>
<tr><td colspan="2"><h2>Static Public Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">static const int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a364d3e56a0749a90cc5de2ac378e6863">READ_FAILED</a> = -99999</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">magic value used on alternate register read interfaces <a href="#a364d3e56a0749a90cc5de2ac378e6863"></a><br/></td></tr>
<tr><td colspan="2"><h2>Protected Member Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#afaae41796f1468062d4ad237322baf9e">shutdown_daughterboards</a> ()</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a9d4d1ef184ad622c7f84a6f940614b9b">init_db</a> (<a class="el" href="db__base_8h.html#a4847231f7e2f85d0a0f4a5ed78b25ee7">usrp_basic_sptr</a> u)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">One time call, made only only from usrp_standard_*make after shared_ptr is created. <a href="#a9d4d1ef184ad622c7f84a6f940614b9b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ac72f072eb9220e798019b60b3fe48af6">usrp_basic</a> (int which_board, <a class="el" href="structusb__dev__handle.html">libusb_device_handle</a> *open_interface(<a class="el" href="libusb__types_8h.html#a6a41e56fed0168fbd7abd9359c805bf1">libusb_device</a> *dev), const std::string fpga_filename="", const std::string firmware_filename="")</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a77535750946e7d8443a76941a9611cae">set_usb_data_rate</a> (int usb_data_rate)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">advise <a class="el" href="classusrp__basic.html" title="abstract base class for usrp operations">usrp_basic</a> of usb data rate (bytes/sec) <a href="#a77535750946e7d8443a76941a9611cae"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ab8870a35e0bdc63ee6655b5264a6d142">_write_aux_dac</a> (int slot, int which_dac, int value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Write auxiliary digital to analog converter. <a href="#ab8870a35e0bdc63ee6655b5264a6d142"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a8f92d2e9630ec614eedc61858756cce1">_read_aux_adc</a> (int slot, int which_adc, int *value)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a8f92d2e9630ec614eedc61858756cce1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a2aadef5c105459794b22a135730e7480">_read_aux_adc</a> (int slot, int which_adc)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Read auxiliary analog to digital converter. <a href="#a2aadef5c105459794b22a135730e7480"></a><br/></td></tr>
<tr><td colspan="2"><h2>Protected Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="structusb__dev__handle.html">libusb_device_handle</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#aad5f6f17a9fde484c67e7dbdd0491f74">d_udh</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">struct libusb_context * </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a747a3cfca6d00b8d2960b4692ae36bc2">d_ctx</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a4e5297f0010c8f39cfe4fff838b113a4">d_usb_data_rate</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a1d6b6839b9ba385d93684c3497c3fb16">d_bytes_per_poll</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a6d0fecbe64f35fef20293c27dc33a0b0">d_verbose</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">long </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#afa81d2ee842dd6eef04c422276f52d1d">d_fpga_master_clock_freq</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#af3d08c8bcdd0ed116e76ffa5449004f2">d_fpga_shadows</a> [<a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">MAX_REGS</a>]</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#a686ea66e3f43c9ab6df60bd80f41ac3b">d_dbid</a> [2]</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">std::vector< std::vector<br class="typebreak"/>
< <a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> > > </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#aa45df525ed16ee0c885a4972ac7908b4">d_db</a></td></tr>
<tr><td colspan="2"><h2>Static Protected Attributes</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">static const int </td><td class="memItemRight" valign="bottom"><a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">MAX_REGS</a> = 128</td></tr>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>abstract base class for usrp operations </p>
<hr/><h2>Constructor & Destructor Documentation</h2>
<a class="anchor" id="ac72f072eb9220e798019b60b3fe48af6"></a><!-- doxytag: member="usrp_basic::usrp_basic" ref="ac72f072eb9220e798019b60b3fe48af6" args="(int which_board, libusb_device_handle *open_interface(libusb_device *dev), const std::string fpga_filename="", const std::string firmware_filename="")" -->
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<td class="memname">usrp_basic::usrp_basic </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_board</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="structusb__dev__handle.html">libusb_device_handle</a> * </td>
<td class="paramname"> <em>open_interface</em>libusb_device *dev, </td>
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<td class="paramtype">const std::string </td>
<td class="paramname"> <em>fpga_filename</em> = <code>""</code>, </td>
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<td class="paramname"> <em>firmware_filename</em> = <code>""</code></td><td> </td>
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<td>)</td>
<td></td><td></td><td><code> [protected]</code></td>
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<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, <a class="el" href="usrp__basic_8h_source.html#l00070">d_ctx</a>, <a class="el" href="usrp__basic_8h_source.html#l00077">d_fpga_shadows</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00926">usrp_9862_write_many_all()</a>, <a class="el" href="usrp__prims__libusb0_8cc_source.html#l00126">usrp_find_device()</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00111">usrp_hw_rev()</a>, <a class="el" href="usrp__prims__common_8cc_source.html#l00734">usrp_load_standard_bits()</a>, <a class="el" href="usrp__prims__libusb0_8cc_source.html#l00096">usrp_one_time_init()</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00128">usrp_usrp_p()</a>.</p>
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<a class="anchor" id="a01313a5f1c8e0eea1a1ff26388e25f78"></a><!-- doxytag: member="usrp_basic::~usrp_basic" ref="a01313a5f1c8e0eea1a1ff26388e25f78" args="()" -->
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<td class="memname">usrp_basic::~usrp_basic </td>
<td>(</td>
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<td> ) </td>
<td><code> [virtual]</code></td>
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<p>References <a class="el" href="usrp__basic_8h_source.html#l00070">d_ctx</a>, <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, <a class="el" href="usrp__prims__libusb0_8cc_source.html#l00200">usrp_close_interface()</a>, and <a class="el" href="usrp__prims__libusb0_8cc_source.html#l00109">usrp_deinit()</a>.</p>
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<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a09ce78134eea035e42464123356096e4"></a><!-- doxytag: member="usrp_basic::_common_write_oe" ref="a09ce78134eea035e42464123356096e4" args="(txrx_t txrx, int which_side, int value, int mask)" -->
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<td class="memname">bool usrp_basic::_common_write_oe </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
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<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
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<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
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<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
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<td>)</td>
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<p>Write direction register(output enables) for pins that go to daughterboard. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which size </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg</td></tr>
</table>
</dd>
</dl>
<p>Each d'board has 16-bits of general purpose i/o. Setting the bit makes it an output from the FPGA to the d'board.</p>
<p>This register is initialized based on a value stored in the d'board EEPROM. In general, you shouldn't be using this routine without a very good reason. Using this method incorrectly will kill your USRP motherboard and/or daughterboard. </p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01471">usrp_basic_tx::_write_oe()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01064">usrp_basic_rx::_write_oe()</a>, <a class="el" href="db__xcvr2450_8cc_source.html#l00397">xcvr2450::set_gpio()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00167">xcvr2450::xcvr2450()</a>.</p>
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<a class="anchor" id="ad28278c9ff7a33b3a151c561ab037b9f"></a><!-- doxytag: member="usrp_basic::_read_9862" ref="ad28278c9ff7a33b3a151c561ab037b9f" args="(int which_codec, int regno) const " -->
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<td class="memname">int usrp_basic::_read_9862 </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_codec</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td> const</td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Read AD9862 register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_codec</em> </td><td>0 or 1 </td></tr>
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>6-bit register number </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>register value if successful, else READ_FAILED </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00439">_read_9862()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00202">READ_FAILED</a>.</p>
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<a class="anchor" id="a3814dc28edce07e3b5cb48bb3ebdf244"></a><!-- doxytag: member="usrp_basic::_read_9862" ref="a3814dc28edce07e3b5cb48bb3ebdf244" args="(int which_codec, int regno, unsigned char *value) const " -->
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<td class="memname">bool usrp_basic::_read_9862 </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_codec</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">unsigned char * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td> const</td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Read AD9862 register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_codec</em> </td><td>0 or 1 </td></tr>
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>6-bit register number </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>8-bit value </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00895">usrp_9862_read()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00445">_read_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00585">common_pga()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00557">common_set_pga()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00338">set_adc_buffer_bypass()</a>.</p>
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<a class="anchor" id="a2aadef5c105459794b22a135730e7480"></a><!-- doxytag: member="usrp_basic::_read_aux_adc" ref="a2aadef5c105459794b22a135730e7480" args="(int slot, int which_adc)" -->
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<td class="memname">int usrp_basic::_read_aux_adc </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>slot</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [protected]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>slot</em> </td><td>2-bit slot number. E.g., SLOT_TX_A </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value in the range [0,4095] if successful, else READ_FAILED. </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00242">_read_aux_adc()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00202">READ_FAILED</a>.</p>
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<a class="anchor" id="a8f92d2e9630ec614eedc61858756cce1"></a><!-- doxytag: member="usrp_basic::_read_aux_adc" ref="a8f92d2e9630ec614eedc61858756cce1" args="(int slot, int which_adc, int *value)" -->
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<td class="memname">bool usrp_basic::_read_aux_adc </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>slot</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [protected]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>slot</em> </td><td>2-bit slot number. E.g., SLOT_TX_A </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>return 12-bit value [0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l01078">usrp_read_aux_adc()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00248">_read_aux_adc()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00736">common_read_aux_adc()</a>.</p>
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<a class="anchor" id="abf1f167a1c96dd0ed4589afc6c9fad6c"></a><!-- doxytag: member="usrp_basic::_read_fpga_reg" ref="abf1f167a1c96dd0ed4589afc6c9fad6c" args="(int regno)" -->
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<td class="memname">int usrp_basic::_read_fpga_reg </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em></td>
<td> ) </td>
<td></td>
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<div class="memdoc">
<p>Read FPGA register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>7-bit register number </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>register value if successful, else READ_FAILED </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00411">_read_fpga_reg()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00202">READ_FAILED</a>.</p>
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<a class="anchor" id="a4fa26bd8164bd5782adf7fbe00b3d411"></a><!-- doxytag: member="usrp_basic::_read_fpga_reg" ref="a4fa26bd8164bd5782adf7fbe00b3d411" args="(int regno, int *value)" -->
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<td class="memname">bool usrp_basic::_read_fpga_reg </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<div class="memdoc">
<p>Read FPGA register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>7-bit register number </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>32-bit value </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00503">usrp_read_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00417">_read_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00659">common_read_io()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00260">usrp_standard_common::usrp_standard_common()</a>.</p>
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<a class="anchor" id="a9b54622fec87c2ed9c7808078931371f"></a><!-- doxytag: member="usrp_basic::_read_spi" ref="a9b54622fec87c2ed9c7808078931371f" args="(int optional_header, int enables, int format, int len)" -->
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<td class="memname">std::string usrp_basic::_read_spi </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>optional_header</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>enables</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>format</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>len</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00863">usrp_spi_read()</a>.</p>
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<a class="anchor" id="a4585f9c7df7084a6acb29bd6d7950892"></a><!-- doxytag: member="usrp_basic::_set_led" ref="a4585f9c7df7084a6acb29bd6d7950892" args="(int which_led, bool on)" -->
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<td class="memname">bool usrp_basic::_set_led </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_led</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>on</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00406">usrp_set_led()</a>.</p>
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<a class="anchor" id="a8a25444c83f59f7517d0ff687d2ff053"></a><!-- doxytag: member="usrp_basic::_write_9862" ref="a8a25444c83f59f7517d0ff687d2ff053" args="(int which_codec, int regno, unsigned char value)" -->
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<td class="memname">bool usrp_basic::_write_9862 </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_codec</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">unsigned char </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<div class="memdoc">
<p>Write AD9862 register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_codec</em> </td><td>0 or 1 </td></tr>
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>6-bit register number </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>8-bit value </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, <a class="el" href="usrp__basic_8h_source.html#l00073">d_verbose</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00877">usrp_9862_write()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00557">common_set_pga()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00338">set_adc_buffer_bypass()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00315">set_dac_offset()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l01018">usrp_standard_tx::set_tx_freq()</a>.</p>
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<a class="anchor" id="ab8870a35e0bdc63ee6655b5264a6d142"></a><!-- doxytag: member="usrp_basic::_write_aux_dac" ref="ab8870a35e0bdc63ee6655b5264a6d142" args="(int slot, int which_dac, int value)" -->
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<td class="memname">bool usrp_basic::_write_aux_dac </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>slot</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_dac</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [protected]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Write auxiliary digital to analog converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>slot</em> </td><td>Which Tx or Rx slot to write. N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_dac</em> </td><td>[0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>[0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l01047">usrp_write_aux_dac()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00730">common_write_aux_dac()</a>.</p>
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<a class="anchor" id="ac5bdb9be69f27eb3a0530cba9536d0f4"></a><!-- doxytag: member="usrp_basic::_write_fpga_reg" ref="ac5bdb9be69f27eb3a0530cba9536d0f4" args="(int regno, int value)" -->
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<td class="memname">bool usrp_basic::_write_fpga_reg </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Write FPGA register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>7-bit register number </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>32-bit value </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00077">d_fpga_shadows</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, <a class="el" href="usrp__basic_8h_source.html#l00073">d_verbose</a>, <a class="el" href="usrp__basic_8h_source.html#l00076">MAX_REGS</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00491">usrp_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00639">_common_write_oe()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00700">common_write_atr_mask()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00720">common_write_atr_rxval()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00710">common_write_atr_txval()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00649">common_write_io()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00690">common_write_refclk()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00986">usrp_basic_rx::probe_rx_slots()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01393">usrp_basic_tx::probe_tx_slots()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00306">set_adc_offset()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00371">set_dc_offset_cl_enable()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00688">usrp_standard_rx::set_ddc_phase()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00404">usrp_standard_rx::set_decim_rate()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00715">usrp_standard_rx::set_format()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00682">usrp_standard_rx::set_fpga_mode()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00908">usrp_basic_rx::set_fpga_rx_sample_rate_divisor()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01308">usrp_basic_tx::set_fpga_tx_sample_rate_divisor()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00897">usrp_standard_tx::set_interp_rate()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00650">usrp_standard_rx::set_rx_freq()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00102">usrp_basic()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00488">write_atr_rx_delay()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00482">write_atr_tx_delay()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00942">usrp_standard_tx::write_hw_mux_reg()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00530">usrp_standard_rx::write_hw_mux_reg()</a>.</p>
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<a class="anchor" id="a0c200dc2d39d68d7a77e92859c5228a0"></a><!-- doxytag: member="usrp_basic::_write_fpga_reg_masked" ref="a0c200dc2d39d68d7a77e92859c5228a0" args="(int regno, int value, int mask)" -->
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<td class="memname">bool usrp_basic::_write_fpga_reg_masked </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>regno</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Write FPGA register with mask. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>regno</em> </td><td>7-bit register number </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>16-bit value </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>16-bit value </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true if successful Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00077">d_fpga_shadows</a>, <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, <a class="el" href="usrp__basic_8h_source.html#l00073">d_verbose</a>, <a class="el" href="usrp__basic_8h_source.html#l00076">MAX_REGS</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00491">usrp_write_fpga_reg()</a>.</p>
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<a class="anchor" id="ac540c04b719f1ce30426ecb2214107ef"></a><!-- doxytag: member="usrp_basic::_write_oe" ref="ac540c04b719f1ce30426ecb2214107ef" args="(int which_side, int value, int mask)=0" -->
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<td class="memname">virtual bool usrp_basic::_write_oe </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Write direction register (output enables) for pins that go to daughterboard. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which size </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg</td></tr>
</table>
</dd>
</dl>
<p>Each d'board has 16-bits of general purpose i/o. Setting the bit makes it an output from the FPGA to the d'board.</p>
<p>This register is initialized based on a value stored in the d'board EEPROM. In general, you shouldn't be using this routine without a very good reason. Using this method incorrectly will kill your USRP motherboard and/or daughterboard. </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a83f39a101787d86a0850e72499286c00">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a0ecdfcb63c28d66b2f036156e33f20d8">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00222">db_base::_enable_refclk()</a>, <a class="el" href="db__bitshark__rx_8cc_source.html#l00121">db_bitshark_rx::db_bitshark_rx()</a>, <a class="el" href="db__dbs__rx_8cc_source.html#l00034">db_dbs_rx::db_dbs_rx()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00041">flexrf_base::flexrf_base()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00370">flexrf_base_rx::flexrf_base_rx()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00251">flexrf_base_tx::flexrf_base_tx()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00049">wbxng_base::wbxng_base()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00302">wbxng_base_rx::wbxng_base_rx()</a>, and <a class="el" href="db__wbxng_8cc_source.html#l00149">wbxng_base_tx::wbxng_base_tx()</a>.</p>
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<a class="anchor" id="aaf100fafc406ef75faafcf3e38df7849"></a><!-- doxytag: member="usrp_basic::_write_spi" ref="aaf100fafc406ef75faafcf3e38df7849" args="(int optional_header, int enables, int format, std::string buf)" -->
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<td class="memname">bool usrp_basic::_write_spi </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>optional_header</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>enables</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>format</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">std::string </td>
<td class="paramname"> <em>buf</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<div class="memdoc">
<p>Write data to SPI bus peripheral. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>optional_header</em> </td><td>0,1 or 2 bytes to write before buf. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>enables</em> </td><td>bitmask of peripherals to write. See usrp_spi_defs.h </td></tr>
<tr><td valign="top"></td><td valign="top"><em>format</em> </td><td>transaction format. See usrp_spi_defs.h SPI_FMT_* </td></tr>
<tr><td valign="top"></td><td valign="top"><em>buf</em> </td><td>the data to write </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful Writes are limited to a maximum of 64 bytes.</dd></dl>
<p>If <code>format</code> specifies that optional_header bytes are present, they are written to the peripheral immediately prior to writing <code>buf</code>. </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00848">usrp_spi_write()</a>.</p>
<p>Referenced by <a class="el" href="db__flexrf_8cc_source.html#l00113">flexrf_base::_write_it()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00381">xcvr2450::send_reg()</a>.</p>
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<a class="anchor" id="a1f769dc9ea28d701fa2f7da2be82325d"></a><!-- doxytag: member="usrp_basic::block_size" ref="a1f769dc9ea28d701fa2f7da2be82325d" args="() const =0" -->
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<td class="memname">virtual int usrp_basic::block_size </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
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<div class="memdoc">
<p>returns current fusb block size </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#ab42bca6a45be1e18e074b494905db7db">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a3d88f6bddfb24f2ad375b65b935ac6e9">usrp_basic_tx</a>.</p>
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<a class="anchor" id="ac25d56e74572309a87397f0fce1a102b"></a><!-- doxytag: member="usrp_basic::common_pga" ref="ac25d56e74572309a87397f0fce1a102b" args="(txrx_t txrx, int which_amp) const " -->
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<td class="memname">double usrp_basic::common_pga </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td> const</td>
</tr>
</table>
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<p>Return programmable gain amplifier gain setting in dB. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00439">_read_9862()</a>, <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, <a class="el" href="classusrp__basic.html#ae67abb570f10f1216c001f2409fe3331">pga_db_per_step()</a>, <a class="el" href="classusrp__basic.html#afcab635a411c57f16820e44a83bfe259">pga_min()</a>, <a class="el" href="usrp__basic_8h_source.html#l00202">READ_FAILED</a>, <a class="el" href="ad9862_8h_source.html#l00047">REG_RX_A</a>, <a class="el" href="ad9862_8h_source.html#l00048">REG_RX_B</a>, and <a class="el" href="ad9862_8h_source.html#l00093">REG_TX_PGA</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01447">usrp_basic_tx::pga()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01040">usrp_basic_rx::pga()</a>.</p>
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<a class="anchor" id="a06cfd0e5675618f773c5466bd235a369"></a><!-- doxytag: member="usrp_basic::common_pga_db_per_step" ref="a06cfd0e5675618f773c5466bd235a369" args="(txrx_t txrx) const " -->
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<td class="memname">double usrp_basic::common_pga_db_per_step </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em></td>
<td> ) </td>
<td> const</td>
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</table>
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<p>Return hardware step size of PGA(linear in dB). </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00557">common_set_pga()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01465">usrp_basic_tx::pga_db_per_step()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01058">usrp_basic_rx::pga_db_per_step()</a>.</p>
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<a class="anchor" id="a7dd5c384b9d2cd4e412939c3b7b7ac79"></a><!-- doxytag: member="usrp_basic::common_pga_max" ref="a7dd5c384b9d2cd4e412939c3b7b7ac79" args="(txrx_t txrx) const " -->
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<td class="memname">double usrp_basic::common_pga_max </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em></td>
<td> ) </td>
<td> const</td>
</tr>
</table>
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<p>Return maximum legal PGA gain in dB. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00557">common_set_pga()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01459">usrp_basic_tx::pga_max()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01052">usrp_basic_rx::pga_max()</a>.</p>
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<a class="anchor" id="a95453e5bb4d0ed4c05b1ea64c880170a"></a><!-- doxytag: member="usrp_basic::common_pga_min" ref="a95453e5bb4d0ed4c05b1ea64c880170a" args="(txrx_t txrx) const " -->
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<td class="memname">double usrp_basic::common_pga_min </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em></td>
<td> ) </td>
<td> const</td>
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</table>
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<p>Return minimum legal PGA gain in dB. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00557">common_set_pga()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01453">usrp_basic_tx::pga_min()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01046">usrp_basic_rx::pga_min()</a>.</p>
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<a class="anchor" id="ab84d66e92dc16fdc104fae9341f1e64f"></a><!-- doxytag: member="usrp_basic::common_read_aux_adc" ref="ab84d66e92dc16fdc104fae9341f1e64f" args="(txrx_t txrx, int which_side, int which_adc)" -->
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<td class="memname">int usrp_basic::common_read_aux_adc </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
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<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
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<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em></td><td> </td>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value in the range [0,4095] if successful, else READ_FAILED. </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00242">_read_aux_adc()</a>.</p>
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<a class="anchor" id="a37bd03473a98cf3776f1988914c1a5ce"></a><!-- doxytag: member="usrp_basic::common_read_aux_adc" ref="a37bd03473a98cf3776f1988914c1a5ce" args="(txrx_t txrx, int which_side, int which_adc, int *value)" -->
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<td class="memname">bool usrp_basic::common_read_aux_adc </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<div class="memdoc">
<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>return 12-bit value [0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00242">_read_aux_adc()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01525">usrp_basic_tx::read_aux_adc()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01118">usrp_basic_rx::read_aux_adc()</a>.</p>
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<a class="anchor" id="a217f6865ef04d1111c2c1d3e7b4260f5"></a><!-- doxytag: member="usrp_basic::common_read_io" ref="a217f6865ef04d1111c2c1d3e7b4260f5" args="(txrx_t txrx, int which_side)" -->
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<td class="memname">int usrp_basic::common_read_io </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<div class="memdoc">
<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>register value if successful, else READ_FAILED </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00659">common_read_io()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00202">READ_FAILED</a>.</p>
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<a class="anchor" id="af7e33b5762cd9c80a714806fa6fa2244"></a><!-- doxytag: member="usrp_basic::common_read_io" ref="af7e33b5762cd9c80a714806fa6fa2244" args="(txrx_t txrx, int which_side, int *value)" -->
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<td class="memname">bool usrp_basic::common_read_io </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<div class="memdoc">
<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>output </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00411">_read_fpga_reg()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00681">common_read_io()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01483">usrp_basic_tx::read_io()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01076">usrp_basic_rx::read_io()</a>.</p>
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<a class="anchor" id="a52f96a90c91ed6e74bfc6a91691a7fa2"></a><!-- doxytag: member="usrp_basic::common_set_pga" ref="a52f96a90c91ed6e74bfc6a91691a7fa2" args="(txrx_t txrx, int which_amp, double gain_in_db)" -->
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<td class="memname">bool usrp_basic::common_set_pga </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">double </td>
<td class="paramname"> <em>gain_in_db</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Set Programmable Gain Amplifier(PGA). </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>gain_in_db</em> </td><td>gain value(linear in dB)</td></tr>
</table>
</dd>
</dl>
<p>gain is rounded to closest setting supported by hardware.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff sucessful.</dd></dl>
<dl class="see"><dt><b>See also:</b></dt><dd><a class="el" href="classusrp__basic.html#afcab635a411c57f16820e44a83bfe259" title="Return minimum legal PGA gain in dB.">pga_min()</a>, <a class="el" href="classusrp__basic.html#ae6a0027c59862dcc2d4da73d50b6a598" title="Return maximum legal PGA gain in dB.">pga_max()</a>, <a class="el" href="classusrp__basic.html#ae67abb570f10f1216c001f2409fe3331" title="Return hardware step size of PGA (linear in dB).">pga_db_per_step()</a> </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00439">_read_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00426">_write_9862()</a>, <a class="el" href="usrp__basic_8h_source.html#l00039">C_TX</a>, <a class="el" href="usrp__basic_8cc_source.html#l00630">common_pga_db_per_step()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00621">common_pga_max()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00612">common_pga_min()</a>, <a class="el" href="ad9862_8h_source.html#l00047">REG_RX_A</a>, <a class="el" href="ad9862_8h_source.html#l00048">REG_RX_B</a>, <a class="el" href="ad9862_8h_source.html#l00093">REG_TX_PGA</a>, and <a class="el" href="ad9862_8h_source.html#l00049">RX_X_BYPASS_INPUT_BUFFER</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01441">usrp_basic_tx::set_pga()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01034">usrp_basic_rx::set_pga()</a>.</p>
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<a class="anchor" id="a0997e93568c71e5432c2445b1ebcc991"></a><!-- doxytag: member="usrp_basic::common_write_atr_mask" ref="a0997e93568c71e5432c2445b1ebcc991" args="(txrx_t txrx, int which_side, int value)" -->
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<td class="memname">bool usrp_basic::common_write_atr_mask </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Automatic Transmit/Receive switching. </p>
<pre></pre><pre> If automatic transmit/receive (ATR) switching is enabled in the
FR_ATR_CTL register, the presence or absence of data in the FPGA
transmit fifo selects between two sets of values for each of the 4
banks of daughterboard i/o pins.</pre><pre> Each daughterboard slot has 3 16-bit registers associated with it:
FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*</pre><pre> FR_ATR_MASK_{0,1,2,3}:</pre><pre> These registers determine which of the daugherboard i/o pins are
affected by ATR switching. If a bit in the mask is set, the
corresponding i/o bit is controlled by ATR, else it's output
value comes from the normal i/o pin output register:
FR_IO_{0,1,2,3}.</pre><pre> FR_ATR_TXVAL_{0,1,2,3}:
FR_ATR_RXVAL_{0,1,2,3}:</pre><pre> If the Tx fifo contains data, then the bits from TXVAL that are
selected by MASK are output. Otherwise, the bits from RXVAL that
are selected by MASK are output.
</pre>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__xcvr2450_8cc_source.html#l00397">xcvr2450::set_gpio()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01501">usrp_basic_tx::write_atr_mask()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01094">usrp_basic_rx::write_atr_mask()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00167">xcvr2450::xcvr2450()</a>.</p>
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<a class="anchor" id="a89eda6a96bc7f4d2d634da793eccbc20"></a><!-- doxytag: member="usrp_basic::common_write_atr_rxval" ref="a89eda6a96bc7f4d2d634da793eccbc20" args="(txrx_t txrx, int which_side, int value)" -->
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<td class="memname">bool usrp_basic::common_write_atr_rxval </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
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<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__xcvr2450_8cc_source.html#l00397">xcvr2450::set_gpio()</a>, <a class="el" href="db__xcvr2450_8cc_source.html#l00251">xcvr2450::shutdown()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01513">usrp_basic_tx::write_atr_rxval()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01106">usrp_basic_rx::write_atr_rxval()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00167">xcvr2450::xcvr2450()</a>.</p>
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<a class="anchor" id="a26e38a0f9f98390b712709812e3387af"></a><!-- doxytag: member="usrp_basic::common_write_atr_txval" ref="a26e38a0f9f98390b712709812e3387af" args="(txrx_t txrx, int which_side, int value)" -->
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<td class="memname">bool usrp_basic::common_write_atr_txval </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
</table>
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<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__xcvr2450_8cc_source.html#l00397">xcvr2450::set_gpio()</a>, <a class="el" href="db__xcvr2450_8cc_source.html#l00251">xcvr2450::shutdown()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01507">usrp_basic_tx::write_atr_txval()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01100">usrp_basic_rx::write_atr_txval()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00167">xcvr2450::xcvr2450()</a>.</p>
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<a class="anchor" id="ac7354a9c4f7e961cb1b541c970a8d009"></a><!-- doxytag: member="usrp_basic::common_write_aux_dac" ref="ac7354a9c4f7e961cb1b541c970a8d009" args="(txrx_t txrx, int which_side, int which_dac, int value)" -->
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<td class="memname">bool usrp_basic::common_write_aux_dac </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_dac</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Write auxiliary digital to analog converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_dac</em> </td><td>[2,3] TX slots must use only 2 and 3. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>[0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00236">_write_aux_dac()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01519">usrp_basic_tx::write_aux_dac()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01112">usrp_basic_rx::write_aux_dac()</a>.</p>
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<a class="anchor" id="acf3120592af4df79d38d253c98c633ae"></a><!-- doxytag: member="usrp_basic::common_write_io" ref="acf3120592af4df79d38d253c98c633ae" args="(txrx_t txrx, int which_side, int value, int mask)" -->
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<td class="memname">bool usrp_basic::common_write_io </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Write daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__xcvr2450_8cc_source.html#l00397">xcvr2450::set_gpio()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00403">flexrf_base_rx::shutdown()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01477">usrp_basic_tx::write_io()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01070">usrp_basic_rx::write_io()</a>, and <a class="el" href="db__xcvr2450_8cc_source.html#l00167">xcvr2450::xcvr2450()</a>.</p>
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<a class="anchor" id="ad673bc49b311e29ab01727c5933ea028"></a><!-- doxytag: member="usrp_basic::common_write_refclk" ref="ad673bc49b311e29ab01727c5933ea028" args="(txrx_t txrx, int which_side, int value)" -->
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<td class="memname">bool usrp_basic::common_write_refclk </td>
<td>(</td>
<td class="paramtype"><a class="el" href="usrp__basic_8h.html#a62f19b5a3751ce085242fa46f8761f71">txrx_t</a> </td>
<td class="paramname"> <em>txrx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Write daughterboard refclk config register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>txrx</em> </td><td>Tx or Rx? </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register, see below</td></tr>
</table>
</dd>
</dl>
<pre>
Control whether a reference clock is sent to the daughterboards,
and what frequency. The refclk is sent on d'board i/o pin 0.</pre><pre> 3 2 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------------------------------------------+-+------------+
| Reserved (Must be zero) |E| DIVISOR |
+-----------------------------------------------+-+------------+</pre><pre> Bit 7 -- 1 turns on refclk, 0 allows IO use
Bits 6:0 Divider value
</pre>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01495">usrp_basic_tx::write_refclk()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01088">usrp_basic_rx::write_refclk()</a>.</p>
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<a class="anchor" id="a551a0912d265427e595ba826858cf3d0"></a><!-- doxytag: member="usrp_basic::converter_rate" ref="a551a0912d265427e595ba826858cf3d0" args="() const =0" -->
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<td class="memname">virtual long usrp_basic::converter_rate </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>returns A/D or D/A converter rate in Hz </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#afd14b376f2449cfb71865c9980ea2358">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a4eefc136417ea3a75a296c1b6dbbd470">usrp_basic_tx</a>.</p>
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<a class="anchor" id="a6d639e50633c165b23e0c4770b26bec2"></a><!-- doxytag: member="usrp_basic::daughterboard_id" ref="a6d639e50633c165b23e0c4770b26bec2" args="(int which_side) const =0" -->
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<td class="memname">virtual int usrp_basic::daughterboard_id </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
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<div class="memdoc">
<p>Return daughterboard ID for given side [0,1]. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which daughterboard</td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>daughterboard id >= 0 if successful </dd>
<dd>
-1 if no daugherboard </dd>
<dd>
-2 if invalid EEPROM on daughterboard </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a34128f4864ece7fafc011786c42b9994">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a25ef6153080bcd83637c87df6ea1d478">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00064">db_base::dbid()</a>.</p>
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<a class="anchor" id="a9e3dfe1821b5aa2438a014fd7ca579f4"></a><!-- doxytag: member="usrp_basic::db" ref="a9e3dfe1821b5aa2438a014fd7ca579f4" args="(int which_side)" -->
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<td class="memname">std::vector< <a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> > usrp_basic::db </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td>
<td> ) </td>
<td></td>
</tr>
</table>
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<div class="memdoc">
<p>Return a vector of size >= 1 that contains shared pointers to the daughterboard instance(s) associated with the specified side.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which daughterboard</td></tr>
</table>
</dd>
</dl>
<p>It is an error to use the returned objects after the <a class="el" href="classusrp__basic.html" title="abstract base class for usrp operations">usrp_basic</a> object has been destroyed. </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>.</p>
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<a class="anchor" id="a8eb1f58ca819437d7f43ad87574bd6da"></a><!-- doxytag: member="usrp_basic::db" ref="a8eb1f58ca819437d7f43ad87574bd6da" args="() const " -->
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<td class="memname">std::vector<std::vector<<a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a>> > usrp_basic::db </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline]</code></td>
</tr>
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<div class="memdoc">
<p>Return a vector of vectors that contain shared pointers to the daughterboard instance(s) associated with the specified side.</p>
<p>It is an error to use the returned objects after the <a class="el" href="classusrp__basic.html" title="abstract base class for usrp operations">usrp_basic</a> object has been destroyed. </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00539">usrp_standard_rx::determine_rx_mux_value()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00951">usrp_standard_tx::determine_tx_mux_value()</a>.</p>
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<a class="anchor" id="a244d4aa01bb6a054cd5bd0998ce2a09a"></a><!-- doxytag: member="usrp_basic::fpga_master_clock_freq" ref="a244d4aa01bb6a054cd5bd0998ce2a09a" args="() const " -->
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<td class="memname">long usrp_basic::fpga_master_clock_freq </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline]</code></td>
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<div class="memdoc">
<p>return frequency of master oscillator on USRP </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00074">d_fpga_master_clock_freq</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00216">db_base::_refclk_freq()</a>, <a class="el" href="usrp__basic_8h_source.html#l00963">usrp_basic_tx::converter_rate()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00848">usrp_basic_rx::converter_rate()</a>.</p>
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<a class="anchor" id="a9d4d1ef184ad622c7f84a6f940614b9b"></a><!-- doxytag: member="usrp_basic::init_db" ref="a9d4d1ef184ad622c7f84a6f940614b9b" args="(usrp_basic_sptr u)" -->
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<td class="memname">void usrp_basic::init_db </td>
<td>(</td>
<td class="paramtype"><a class="el" href="db__base_8h.html#a4847231f7e2f85d0a0f4a5ed78b25ee7">usrp_basic_sptr</a> </td>
<td class="paramname"> <em>u</em></td>
<td> ) </td>
<td><code> [protected]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>One time call, made only only from usrp_standard_*make after shared_ptr is created. </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>, <a class="el" href="usrp__basic_8h_source.html#l00079">d_dbid</a>, and <a class="el" href="db__boards_8cc_source.html#l00043">instantiate_dbs()</a>.</p>
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<a class="anchor" id="a61af504df443a9d846ecf909871f1481"></a><!-- doxytag: member="usrp_basic::is_valid" ref="a61af504df443a9d846ecf909871f1481" args="(const usrp_subdev_spec &ss)" -->
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<td class="memname">bool usrp_basic::is_valid </td>
<td>(</td>
<td class="paramtype">const <a class="el" href="structusrp__subdev__spec.html">usrp_subdev_spec</a> & </td>
<td class="paramname"> <em>ss</em></td>
<td> ) </td>
<td></td>
</tr>
</table>
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<div class="memdoc">
<p>is the subdev_spec valid? </p>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>, <a class="el" href="usrp__subdev__spec_8h_source.html#l00043">usrp_subdev_spec::side</a>, and <a class="el" href="usrp__subdev__spec_8h_source.html#l00044">usrp_subdev_spec::subdev</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00539">usrp_standard_rx::determine_rx_mux_value()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00951">usrp_standard_tx::determine_tx_mux_value()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00208">selected_subdev()</a>.</p>
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<a class="anchor" id="a731389d216c7232020041f7cecd3d581"></a><!-- doxytag: member="usrp_basic::pga" ref="a731389d216c7232020041f7cecd3d581" args="(int which_amp) const =0" -->
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<td class="memname">virtual double usrp_basic::pga </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Return programmable gain amplifier gain setting in dB. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
</table>
</dd>
</dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a982d36d1f8d64a5bb2604cf04caa22d4">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#aa7764a14b980820287ebe3d50a303fbd">usrp_basic_tx</a>.</p>
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<a class="anchor" id="ae67abb570f10f1216c001f2409fe3331"></a><!-- doxytag: member="usrp_basic::pga_db_per_step" ref="ae67abb570f10f1216c001f2409fe3331" args="() const =0" -->
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<td class="memname">virtual double usrp_basic::pga_db_per_step </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Return hardware step size of PGA (linear in dB). </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a7c570ad5c2cb879f1b9f2073117ecf51">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#ac8f1b5ab8940fba58fe01d64727deb40">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00585">common_pga()</a>, <a class="el" href="db__basic_8cc_source.html#l00180">db_basic_rx::gain_db_per_step()</a>, and <a class="el" href="db__basic_8cc_source.html#l00086">db_basic_tx::gain_db_per_step()</a>.</p>
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<a class="anchor" id="ae6a0027c59862dcc2d4da73d50b6a598"></a><!-- doxytag: member="usrp_basic::pga_max" ref="ae6a0027c59862dcc2d4da73d50b6a598" args="() const =0" -->
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<td class="memname">virtual double usrp_basic::pga_max </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Return maximum legal PGA gain in dB. </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a2089bd929d76f28a620fc66726b525f4">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#ac451445ef6cffdffb9e7817c3885f367">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__wbxng_8cc_source.html#l00495">db_wbxng_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l01120">db_flexrf_400_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l01054">db_flexrf_900_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00988">db_flexrf_1800_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00920">db_flexrf_1200_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00852">db_flexrf_2400_rx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00343">flexrf_base_tx::gain_max()</a>, <a class="el" href="db__basic_8cc_source.html#l00174">db_basic_rx::gain_max()</a>, <a class="el" href="db__basic_8cc_source.html#l00080">db_basic_tx::gain_max()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00337">flexrf_base_tx::gain_min()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00429">wbxng_base_rx::set_gain()</a>, and <a class="el" href="db__flexrf_8cc_source.html#l00491">flexrf_base_rx::set_gain()</a>.</p>
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<a class="anchor" id="afcab635a411c57f16820e44a83bfe259"></a><!-- doxytag: member="usrp_basic::pga_min" ref="afcab635a411c57f16820e44a83bfe259" args="() const =0" -->
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<td class="memname">virtual double usrp_basic::pga_min </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [pure virtual]</code></td>
</tr>
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<div class="memdoc">
<p>Return minimum legal PGA gain in dB. </p>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a984a57196c26958e2927667ab3abe4cf">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a7cae37094ad8d1a0095fc058649829d0">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00585">common_pga()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00489">db_wbxng_rx::gain_min()</a>, <a class="el" href="db__flexrf_8cc_source.html#l01114">db_flexrf_400_rx::gain_min()</a>, <a class="el" href="db__flexrf_8cc_source.html#l01048">db_flexrf_900_rx::gain_min()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00982">db_flexrf_1800_rx::gain_min()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00914">db_flexrf_1200_rx::gain_min()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00846">db_flexrf_2400_rx::gain_min()</a>, <a class="el" href="db__basic_8cc_source.html#l00168">db_basic_rx::gain_min()</a>, and <a class="el" href="db__basic_8cc_source.html#l00074">db_basic_tx::gain_min()</a>.</p>
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<a class="anchor" id="ab8b3158fe7448c951ad78bb54a06f5c5"></a><!-- doxytag: member="usrp_basic::read_aux_adc" ref="ab8b3158fe7448c951ad78bb54a06f5c5" args="(int which_side, int which_adc)=0" -->
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<td class="memname">virtual int usrp_basic::read_aux_adc </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
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<div class="memdoc">
<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value in the range [0,4095] if successful, else READ_FAILED. </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#aedc2bc043ad6fed139274328a39a11be">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a1037a256b87c10e54e5650f80052cdc0">usrp_basic_tx</a>.</p>
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<a class="anchor" id="a7e90fb51366e9d6a8f2c844dbca2798a"></a><!-- doxytag: member="usrp_basic::read_aux_adc" ref="a7e90fb51366e9d6a8f2c844dbca2798a" args="(int which_side, int which_adc, int *value)=0" -->
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<td class="memname">virtual bool usrp_basic::read_aux_adc </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Read auxiliary analog to digital converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>[0,1] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>return 12-bit value [0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#acffe1b022ad3ba669ab2131896ebafbf">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a237f04837e77f428551b6b66217f8d9b">usrp_basic_tx</a>.</p>
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<a class="anchor" id="aefe7a2f10626831304091babff21dc0d"></a><!-- doxytag: member="usrp_basic::read_eeprom" ref="aefe7a2f10626831304091babff21dc0d" args="(int i2c_addr, int eeprom_offset, int len)" -->
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<td class="memname">std::string usrp_basic::read_eeprom </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>i2c_addr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>eeprom_offset</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>len</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
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<p>Read EEPROM on motherboard or any daughterboard. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>i2c_addr</em> </td><td>I2C bus address of EEPROM </td></tr>
<tr><td valign="top"></td><td valign="top"><em>eeprom_offset</em> </td><td>byte offset in EEPROM to begin reading </td></tr>
<tr><td valign="top"></td><td valign="top"><em>len</em> </td><td>number of bytes to read </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>the data read if successful, else a zero length string. </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00985">usrp_eeprom_read()</a>.</p>
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<a class="anchor" id="ab284caa2e15464f62aa80ad1f540ecc5"></a><!-- doxytag: member="usrp_basic::read_i2c" ref="ab284caa2e15464f62aa80ad1f540ecc5" args="(int i2c_addr, int len)" -->
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<td class="memname">std::string usrp_basic::read_i2c </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>i2c_addr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>len</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Read from I2C peripheral. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>i2c_addr</em> </td><td>I2C bus address (7-bits) </td></tr>
<tr><td valign="top"></td><td valign="top"><em>len</em> </td><td>number of bytes to read </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>the data read if successful, else a zero length string. Reads are limited to a maximum of 64 bytes. </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00837">usrp_i2c_read()</a>.</p>
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<a class="anchor" id="a166feedb83f6425d3bbbbf65f29bf42c"></a><!-- doxytag: member="usrp_basic::read_io" ref="a166feedb83f6425d3bbbbf65f29bf42c" args="(int which_side)=0" -->
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<td class="memname">virtual int usrp_basic::read_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em></td>
<td> ) </td>
<td><code> [pure virtual]</code></td>
</tr>
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<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>register value if successful, else READ_FAILED </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a67b0c263712cd5bd56f48e6bd8754bc6">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a98999c00a4d121c09a234b23c63d8b42">usrp_basic_tx</a>.</p>
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<a class="anchor" id="ad443caee9815e7c69a8b39a29cf8846a"></a><!-- doxytag: member="usrp_basic::read_io" ref="ad443caee9815e7c69a8b39a29cf8846a" args="(int which_side, int *value)=0" -->
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<td class="memname">virtual bool usrp_basic::read_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int * </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
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</table>
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<div class="memdoc">
<p>Read daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>output </td></tr>
</table>
</dd>
</dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a275d14df1506faa570fd5cc231a14ee9">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#ad5b21bcc2798026f5a1555e9ca4c899f">usrp_basic_tx</a>.</p>
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<a class="anchor" id="a648de1479d7632b59bf2732f231ddbe0"></a><!-- doxytag: member="usrp_basic::selected_subdev" ref="a648de1479d7632b59bf2732f231ddbe0" args="(const usrp_subdev_spec &ss)" -->
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<td class="memname"><a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a> usrp_basic::selected_subdev </td>
<td>(</td>
<td class="paramtype">const <a class="el" href="structusrp__subdev__spec.html">usrp_subdev_spec</a> & </td>
<td class="paramname"> <em>ss</em></td>
<td> ) </td>
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<p>given a subdev_spec, return the corresponding daughterboard object. </p>
<dl><dt><b>Exceptions:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>std::invalid_</em> </td><td>argument if ss is invalid.</td></tr>
</table>
</dd>
</dl>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>ss</em> </td><td>specifies the side and subdevice </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>, <a class="el" href="usrp__basic_8cc_source.html#l00196">is_valid()</a>, <a class="el" href="usrp__subdev__spec_8h_source.html#l00043">usrp_subdev_spec::side</a>, and <a class="el" href="usrp__subdev__spec_8h_source.html#l00044">usrp_subdev_spec::subdev</a>.</p>
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<a class="anchor" id="a70a71308412a67eaf825c13399faa078"></a><!-- doxytag: member="usrp_basic::serial_number" ref="a70a71308412a67eaf825c13399faa078" args="()" -->
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<td class="memname">std::string usrp_basic::serial_number </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<p>return the usrp's serial number. </p>
<dl class="return"><dt><b>Returns:</b></dt><dd>non-zero length string iff successful. </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l01223">usrp_serial_number()</a>.</p>
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<a class="anchor" id="a97fc801cbafa85040a3d39be03d27a62"></a><!-- doxytag: member="usrp_basic::set_adc_buffer_bypass" ref="a97fc801cbafa85040a3d39be03d27a62" args="(int which_adc, bool bypass)" -->
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<td class="memname">bool usrp_basic::set_adc_buffer_bypass </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>bypass</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Control ADC input buffer. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>which ADC[0,3] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>bypass</em> </td><td>if non-zero, bypass input buffer and connect input directly to switched cap SHA input of RxPGA. </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00439">_read_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00426">_write_9862()</a>, <a class="el" href="ad9862_8h_source.html#l00047">REG_RX_A</a>, <a class="el" href="ad9862_8h_source.html#l00048">REG_RX_B</a>, <a class="el" href="ad9862_8h_source.html#l00037">REG_RX_PWR_DN</a>, <a class="el" href="ad9862_8h_source.html#l00044">RX_PWR_DN_BUF_A</a>, <a class="el" href="ad9862_8h_source.html#l00043">RX_PWR_DN_BUF_B</a>, and <a class="el" href="ad9862_8h_source.html#l00049">RX_X_BYPASS_INPUT_BUFFER</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00088">db_base::bypass_adc_buffers()</a>.</p>
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<a class="anchor" id="ad0e07c8d85aa220aaf150e27dd8b545f"></a><!-- doxytag: member="usrp_basic::set_adc_offset" ref="ad0e07c8d85aa220aaf150e27dd8b545f" args="(int which_adc, int offset)" -->
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<td class="memname">bool usrp_basic::set_adc_offset </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_adc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>offset</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
</tr>
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<p>Set ADC offset correction. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_adc</em> </td><td>which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q... </td></tr>
<tr><td valign="top"></td><td valign="top"><em>offset</em> </td><td>16-bit value to subtract from raw ADC input. </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00986">usrp_basic_rx::probe_rx_slots()</a>.</p>
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<a class="anchor" id="ab18f4a02c0efcac10f8e9406ca7a57a7"></a><!-- doxytag: member="usrp_basic::set_dac_offset" ref="ab18f4a02c0efcac10f8e9406ca7a57a7" args="(int which_dac, int offset, int offset_pin)" -->
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<td class="memname">bool usrp_basic::set_dac_offset </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_dac</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>offset</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>offset_pin</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Set DAC offset correction. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_dac</em> </td><td>which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q... </td></tr>
<tr><td valign="top"></td><td valign="top"><em>offset</em> </td><td>10-bit offset value (ambiguous format: See AD9862 datasheet). </td></tr>
<tr><td valign="top"></td><td valign="top"><em>offset_pin</em> </td><td>1-bit value. If 0 offset applied to -ve differential pin; If 1 offset applied to +ve differential pin. </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00426">_write_9862()</a>, <a class="el" href="ad9862_8h_source.html#l00083">REG_TX_A_OFFSET_HI</a>, <a class="el" href="ad9862_8h_source.html#l00082">REG_TX_A_OFFSET_LO</a>, <a class="el" href="ad9862_8h_source.html#l00085">REG_TX_B_OFFSET_HI</a>, and <a class="el" href="ad9862_8h_source.html#l00084">REG_TX_B_OFFSET_LO</a>.</p>
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<a class="anchor" id="af20cc324fca8d089226d5a6dfc3d3668"></a><!-- doxytag: member="usrp_basic::set_dc_offset_cl_enable" ref="af20cc324fca8d089226d5a6dfc3d3668" args="(int bits, int mask)" -->
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<td class="memname">bool usrp_basic::set_dc_offset_cl_enable </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>bits</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Enable/disable automatic DC offset removal control loop in FPGA. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>bits</em> </td><td>which control loops to enable </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which <code>bits</code> to pay attention to</td></tr>
</table>
</dd>
</dl>
<p>If the corresponding bit is set, enable the automatic DC offset correction control loop.</p>
<pre>
The 4 low bits are significant:</pre><pre> ADC0 = (1 << 0)
ADC1 = (1 << 1)
ADC2 = (1 << 2)
ADC3 = (1 << 3)
</pre><p>By default the control loop is enabled on all ADC's. </p>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00077">d_fpga_shadows</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00765">usrp_basic_rx::usrp_basic_rx()</a>.</p>
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<a class="anchor" id="a825640d1de15253b5bae18762a0e403e"></a><!-- doxytag: member="usrp_basic::set_fpga_master_clock_freq" ref="a825640d1de15253b5bae18762a0e403e" args="(long master_clock)" -->
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<td class="memname">void usrp_basic::set_fpga_master_clock_freq </td>
<td>(</td>
<td class="paramtype">long </td>
<td class="paramname"> <em>master_clock</em></td>
<td> ) </td>
<td><code> [inline]</code></td>
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<p>Tell API that the master oscillator on the USRP is operating at a non-standard fixed frequency. This is only needed for custom USRP hardware modified to operate at a different frequency from the default factory configuration. This function must be called prior to any other API function. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>master_clock</em> </td><td>USRP2 FPGA master clock frequency in Hz (10..64 MHz) </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00074">d_fpga_master_clock_freq</a>.</p>
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<a class="anchor" id="afdcf0497f2554589b36a57806e239a07"></a><!-- doxytag: member="usrp_basic::set_pga" ref="afdcf0497f2554589b36a57806e239a07" args="(int which_amp, double gain_in_db)=0" -->
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<td class="memname">virtual bool usrp_basic::set_pga </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_amp</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">double </td>
<td class="paramname"> <em>gain_in_db</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
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<p>Set Programmable Gain Amplifier (PGA). </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_amp</em> </td><td>which amp [0,3] </td></tr>
<tr><td valign="top"></td><td valign="top"><em>gain_in_db</em> </td><td>gain value (linear in dB)</td></tr>
</table>
</dd>
</dl>
<p>gain is rounded to closest setting supported by hardware.</p>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff sucessful.</dd></dl>
<dl class="see"><dt><b>See also:</b></dt><dd><a class="el" href="classusrp__basic.html#afcab635a411c57f16820e44a83bfe259" title="Return minimum legal PGA gain in dB.">pga_min()</a>, <a class="el" href="classusrp__basic.html#ae6a0027c59862dcc2d4da73d50b6a598" title="Return maximum legal PGA gain in dB.">pga_max()</a>, <a class="el" href="classusrp__basic.html#ae67abb570f10f1216c001f2409fe3331" title="Return hardware step size of PGA (linear in dB).">pga_db_per_step()</a> </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a85804ff6612a34c800a7181ea90de6b4">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a5d950d5f8a8969e17525cee918d9bd06">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__wbxng_8cc_source.html#l00111">wbxng_base::_set_pga()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00213">flexrf_base::_set_pga()</a>, <a class="el" href="db__basic_8cc_source.html#l00186">db_basic_rx::set_gain()</a>, and <a class="el" href="db__basic_8cc_source.html#l00092">db_basic_tx::set_gain()</a>.</p>
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<a class="anchor" id="a77535750946e7d8443a76941a9611cae"></a><!-- doxytag: member="usrp_basic::set_usb_data_rate" ref="a77535750946e7d8443a76941a9611cae" args="(int usb_data_rate)" -->
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<td class="memname">void usrp_basic::set_usb_data_rate </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>usb_data_rate</em></td>
<td> ) </td>
<td><code> [protected]</code></td>
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<p>advise <a class="el" href="classusrp__basic.html" title="abstract base class for usrp operations">usrp_basic</a> of usb data rate (bytes/sec) </p>
<p>N.B., this doesn't tweak any hardware. Derived classes should call this to inform us of the data rate whenever it's first set or if it changes.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>usb_data_rate</em> </td><td>bytes/sec </td></tr>
</table>
</dd>
</dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00072">d_bytes_per_poll</a>, and <a class="el" href="usrp__basic_8h_source.html#l00071">d_usb_data_rate</a>.</p>
<p>Referenced by <a class="el" href="usrp__standard_8cc_source.html#l00404">usrp_standard_rx::set_decim_rate()</a>, and <a class="el" href="usrp__standard_8cc_source.html#l00897">usrp_standard_tx::set_interp_rate()</a>.</p>
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<a class="anchor" id="ae200e6eb7dbbaf81a3c1353a401f97d3"></a><!-- doxytag: member="usrp_basic::set_verbose" ref="ae200e6eb7dbbaf81a3c1353a401f97d3" args="(bool on)" -->
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<td class="memname">void usrp_basic::set_verbose </td>
<td>(</td>
<td class="paramtype">bool </td>
<td class="paramname"> <em>on</em></td>
<td> ) </td>
<td><code> [inline]</code></td>
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<p>References <a class="el" href="usrp__basic_8h_source.html#l00073">d_verbose</a>.</p>
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<a class="anchor" id="afaae41796f1468062d4ad237322baf9e"></a><!-- doxytag: member="usrp_basic::shutdown_daughterboards" ref="afaae41796f1468062d4ad237322baf9e" args="()" -->
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<td class="memname">void usrp_basic::shutdown_daughterboards </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td><code> [protected]</code></td>
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</table>
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<p>References <a class="el" href="usrp__basic_8h_source.html#l00089">d_db</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00830">usrp_basic_rx::~usrp_basic_rx()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01237">usrp_basic_tx::~usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a4291ecf3cc0870baaa12644143182db4"></a><!-- doxytag: member="usrp_basic::start" ref="a4291ecf3cc0870baaa12644143182db4" args="()" -->
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<td class="memname">bool usrp_basic::start </td>
<td>(</td>
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<td> ) </td>
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<p>Start data transfers. Called in base class to derived class order. </p>
<p>Reimplemented in <a class="el" href="classusrp__basic__rx.html#a6097b0d8b2cac9a67237368d1a81b7f4">usrp_basic_rx</a>, <a class="el" href="classusrp__basic__tx.html#a3d16b0d8e96d5124b6392bc44014124d">usrp_basic_tx</a>, <a class="el" href="classusrp__standard__rx.html#ac97772bce1c0aaca0fee2462accd8123">usrp_standard_rx</a>, and <a class="el" href="classusrp__standard__tx.html#ae6f8039f30bf641b937877001127176f">usrp_standard_tx</a>.</p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l01251">usrp_basic_tx::start()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00849">usrp_basic_rx::start()</a>.</p>
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<a class="anchor" id="a69292bbc3b47b5ca85d4c0404dc4a58a"></a><!-- doxytag: member="usrp_basic::stop" ref="a69292bbc3b47b5ca85d4c0404dc4a58a" args="()" -->
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<td class="memname">bool usrp_basic::stop </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td></td>
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<div class="memdoc">
<p>Stop data transfers. Called in base class to derived class order. </p>
<p>Reimplemented in <a class="el" href="classusrp__basic__rx.html#a094cb05d34da15711c6ca5c4b24defe9">usrp_basic_rx</a>, <a class="el" href="classusrp__basic__tx.html#ab1c5851e72e29e86af914da5c7f62cf8">usrp_basic_tx</a>, <a class="el" href="classusrp__standard__rx.html#a545808dbbdc7de3331123e7af6021144">usrp_standard_rx</a>, and <a class="el" href="classusrp__standard__tx.html#a5173292e6162fce54a875683f02cdd5c">usrp_standard_tx</a>.</p>
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<a class="anchor" id="a530c23ff633c630530ec491c368a755d"></a><!-- doxytag: member="usrp_basic::usb_data_rate" ref="a530c23ff633c630530ec491c368a755d" args="() const " -->
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<td class="memname">int usrp_basic::usb_data_rate </td>
<td>(</td>
<td class="paramname"></td>
<td> ) </td>
<td> const<code> [inline]</code></td>
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<dl class="return"><dt><b>Returns:</b></dt><dd>usb data rate in bytes/sec </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00071">d_usb_data_rate</a>.</p>
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<a class="anchor" id="a49074783b3757b6af17ddf8e8f56be6c"></a><!-- doxytag: member="usrp_basic::write_atr_mask" ref="a49074783b3757b6af17ddf8e8f56be6c" args="(int which_side, int value)=0" -->
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<td class="memname">virtual bool usrp_basic::write_atr_mask </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a0974bedf9b0406709e83e839f40e2b36">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a8cfd094ce093e5d46fcad5531ee20570">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00107">db_base::set_atr_mask()</a>.</p>
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<a class="anchor" id="ad9b95b1ca0e2616c1b3808892fdda1b0"></a><!-- doxytag: member="usrp_basic::write_atr_rx_delay" ref="ad9b95b1ca0e2616c1b3808892fdda1b0" args="(int value)" -->
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<td class="memname">bool usrp_basic::write_atr_rx_delay </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td>
<td> ) </td>
<td></td>
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<p>Clock ticks to delay falling edge of T/R signal. </p>
<dl class="see"><dt><b>See also:</b></dt><dd><a class="el" href="classusrp__basic.html#a49074783b3757b6af17ddf8e8f56be6c">write_atr_mask</a>, <a class="el" href="classusrp__basic.html#a504bf45d241c56ddf00ee07fc946207e">write_atr_txval</a>, <a class="el" href="classusrp__basic.html#ae5466590dd7ec5646fefbb82d92ad899">write_atr_rxval</a> </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00136">db_base::set_atr_rx_delay()</a>.</p>
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<a class="anchor" id="ae5466590dd7ec5646fefbb82d92ad899"></a><!-- doxytag: member="usrp_basic::write_atr_rxval" ref="ae5466590dd7ec5646fefbb82d92ad899" args="(int which_side, int value)=0" -->
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<td class="memname">virtual bool usrp_basic::write_atr_rxval </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a7cb8b45ce6815d3ee3c97a064a63e9ee">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a01b222b0ba0a365db87ab74731325d5b">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00121">db_base::set_atr_rxval()</a>.</p>
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<a class="anchor" id="a70f4070830b0db3fd0c3addb97ce966e"></a><!-- doxytag: member="usrp_basic::write_atr_tx_delay" ref="a70f4070830b0db3fd0c3addb97ce966e" args="(int value)" -->
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<td class="memname">bool usrp_basic::write_atr_tx_delay </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td>
<td> ) </td>
<td></td>
</tr>
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<p>Clock ticks to delay rising of T/R signal. </p>
<dl class="see"><dt><b>See also:</b></dt><dd><a class="el" href="classusrp__basic.html#a49074783b3757b6af17ddf8e8f56be6c">write_atr_mask</a>, <a class="el" href="classusrp__basic.html#a504bf45d241c56ddf00ee07fc946207e">write_atr_txval</a>, <a class="el" href="classusrp__basic.html#ae5466590dd7ec5646fefbb82d92ad899">write_atr_rxval</a> </dd></dl>
<p>References <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00128">db_base::set_atr_tx_delay()</a>.</p>
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<a class="anchor" id="a504bf45d241c56ddf00ee07fc946207e"></a><!-- doxytag: member="usrp_basic::write_atr_txval" ref="a504bf45d241c56ddf00ee07fc946207e" args="(int which_side, int value)=0" -->
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<td class="memname">virtual bool usrp_basic::write_atr_txval </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
</tr>
</table>
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<div class="memdoc">
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a914e9b61a4b1441dc955b1dc9cd17742">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#af4c224f2e92a07ded29fc6dedba8c2d7">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00114">db_base::set_atr_txval()</a>.</p>
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<a class="anchor" id="a332790fa84b6b64f82de8983b45b611a"></a><!-- doxytag: member="usrp_basic::write_aux_dac" ref="a332790fa84b6b64f82de8983b45b611a" args="(int which_side, int which_dac, int value)=0" -->
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<td class="memname">virtual bool usrp_basic::write_aux_dac </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_dac</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
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<p>Write auxiliary digital to analog converter. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's. SLOT_TX_B and SLOT_RX_B share the same AUX DAC's. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>which_dac</em> </td><td>[2,3] TX slots must use only 2 and 3. </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>[0,4095] </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful </dd></dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#ae5cbeedfd6df52cdc4b13c87e2521b97">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a2d3f6eda1859921bb7c0f26d2dd1163d">usrp_basic_tx</a>.</p>
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<a class="anchor" id="a3900d37e951b83c938669f5fa0255866"></a><!-- doxytag: member="usrp_basic::write_eeprom" ref="a3900d37e951b83c938669f5fa0255866" args="(int i2c_addr, int eeprom_offset, const std::string buf)" -->
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<td class="memname">bool usrp_basic::write_eeprom </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>i2c_addr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>eeprom_offset</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>buf</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Write EEPROM on motherboard or any daughterboard. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>i2c_addr</em> </td><td>I2C bus address of EEPROM </td></tr>
<tr><td valign="top"></td><td valign="top"><em>eeprom_offset</em> </td><td>byte offset in EEPROM to begin writing </td></tr>
<tr><td valign="top"></td><td valign="top"><em>buf</em> </td><td>the data to write </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff sucessful </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00960">usrp_eeprom_write()</a>.</p>
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<a class="anchor" id="a664e5aa3a3fb8a4c50b752906fcb79a0"></a><!-- doxytag: member="usrp_basic::write_i2c" ref="a664e5aa3a3fb8a4c50b752906fcb79a0" args="(int i2c_addr, const std::string buf)" -->
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<td class="memname">bool usrp_basic::write_i2c </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>i2c_addr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const std::string </td>
<td class="paramname"> <em>buf</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td></td>
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<p>Write to I2C peripheral. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>i2c_addr</em> </td><td>I2C bus address (7-bits) </td></tr>
<tr><td valign="top"></td><td valign="top"><em>buf</em> </td><td>the data to write </td></tr>
</table>
</dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>true iff successful Writes are limited to a maximum of of 64 bytes. </dd></dl>
<p>References <a class="el" href="usrp__basic_8h_source.html#l00069">d_udh</a>, and <a class="el" href="usrp__prims__common_8cc_source.html#l00825">usrp_i2c_write()</a>.</p>
<p>Referenced by <a class="el" href="db__bitshark__rx_8cc_source.html#l00192">db_bitshark_rx::set_bw()</a>, <a class="el" href="db__bitshark__rx_8cc_source.html#l00292">db_bitshark_rx::set_clock_scheme()</a>, and <a class="el" href="db__bitshark__rx_8cc_source.html#l00256">db_bitshark_rx::set_gain()</a>.</p>
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<a class="anchor" id="a75aca6cca672ac2deedf14fb2c04ab0e"></a><!-- doxytag: member="usrp_basic::write_io" ref="a75aca6cca672ac2deedf14fb2c04ab0e" args="(int which_side, int value, int mask)=0" -->
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<td class="memname">virtual bool usrp_basic::write_io </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>mask</em></td><td> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
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<p>Write daughterboard i/o pin value. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register </td></tr>
<tr><td valign="top"></td><td valign="top"><em>mask</em> </td><td>which bits of value to write into reg </td></tr>
</table>
</dd>
</dl>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#a5ab1edec410f1d5399c187cb243905a5">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a19a1a1db062ac7d3d4625c95770353ff">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__wbxng_8cc_source.html#l00459">wbxng_base_rx::_set_attn()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00370">flexrf_base_rx::flexrf_base_rx()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00251">flexrf_base_tx::flexrf_base_tx()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00387">wbxng_base_rx::select_rx_antenna()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00449">flexrf_base_rx::select_rx_antenna()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00225">wbxng_base_tx::set_enable()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00319">flexrf_base_tx::set_enable()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00342">wbxng_base_rx::shutdown()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00184">wbxng_base_tx::shutdown()</a>, <a class="el" href="db__flexrf_8cc_source.html#l00281">flexrf_base_tx::shutdown()</a>, <a class="el" href="db__wbxng_8cc_source.html#l00302">wbxng_base_rx::wbxng_base_rx()</a>, and <a class="el" href="db__wbxng_8cc_source.html#l00149">wbxng_base_tx::wbxng_base_tx()</a>.</p>
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<a class="anchor" id="a80a4f8800742b6b06ec6f1908a448fc8"></a><!-- doxytag: member="usrp_basic::write_refclk" ref="a80a4f8800742b6b06ec6f1908a448fc8" args="(int which_side, int value)=0" -->
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<td class="memname">virtual bool usrp_basic::write_refclk </td>
<td>(</td>
<td class="paramtype">int </td>
<td class="paramname"> <em>which_side</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int </td>
<td class="paramname"> <em>value</em></td><td> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td><td><code> [pure virtual]</code></td>
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</table>
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<p>Write daughterboard refclk config register. </p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>which_side</em> </td><td>[0,1] which d'board </td></tr>
<tr><td valign="top"></td><td valign="top"><em>value</em> </td><td>value to write into register, see below</td></tr>
</table>
</dd>
</dl>
<pre>
Control whether a reference clock is sent to the daughterboards,
and what frequency. The refclk is sent on d'board i/o pin 0.</pre><pre> 3 2 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------------------------------------------+-+------------+
| Reserved (Must be zero) |E| DIVISOR |
+-----------------------------------------------+-+------------+</pre><pre> Bit 7 -- 1 turns on refclk, 0 allows IO use
Bits 6:0 Divider value
</pre>
<p>Implemented in <a class="el" href="classusrp__basic__rx.html#ac6c7387f1bf488ee22c79be22e3f48dd">usrp_basic_rx</a>, and <a class="el" href="classusrp__basic__tx.html#a6076561547b3912ea535334e6e6d4c2f">usrp_basic_tx</a>.</p>
<p>Referenced by <a class="el" href="db__base_8cc_source.html#l00222">db_base::_enable_refclk()</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a1d6b6839b9ba385d93684c3497c3fb16"></a><!-- doxytag: member="usrp_basic::d_bytes_per_poll" ref="a1d6b6839b9ba385d93684c3497c3fb16" args="" -->
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<td class="memname">int <a class="el" href="classusrp__basic.html#a1d6b6839b9ba385d93684c3497c3fb16">usrp_basic::d_bytes_per_poll</a><code> [protected]</code></td>
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<div class="memdoc">
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00923">usrp_basic_rx::read()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00229">set_usb_data_rate()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01323">usrp_basic_tx::write()</a>.</p>
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<a class="anchor" id="a747a3cfca6d00b8d2960b4692ae36bc2"></a><!-- doxytag: member="usrp_basic::d_ctx" ref="a747a3cfca6d00b8d2960b4692ae36bc2" args="" -->
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<td class="memname">struct libusb_context* <a class="el" href="classusrp__basic.html#a747a3cfca6d00b8d2960b4692ae36bc2">usrp_basic::d_ctx</a><code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00102">usrp_basic()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00765">usrp_basic_rx::usrp_basic_rx()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx::usrp_basic_tx()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00157">~usrp_basic()</a>.</p>
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<a class="anchor" id="aa45df525ed16ee0c885a4972ac7908b4"></a><!-- doxytag: member="usrp_basic::d_db" ref="aa45df525ed16ee0c885a4972ac7908b4" args="" -->
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<td class="memname">std::vector< std::vector<<a class="el" href="db__base_8h.html#a61ead10400f658a22128a321e14ae0ac">db_base_sptr</a>> > <a class="el" href="classusrp__basic.html#aa45df525ed16ee0c885a4972ac7908b4">usrp_basic::d_db</a><code> [protected]</code></td>
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<p>Shared pointers to subclasses of <a class="el" href="classdb__base.html" title="Abstract base class for all USRP daughterboards.">db_base</a>.</p>
<p>The outer vector is of length 2 (0 = side A, 1 = side B). The inner vectors are of length 1, 2 or 3 depending on the number of subdevices implemented by the daugherboard. At this time, only the Basic Rx and LF Rx implement more than 1 subdevice. </p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00189">db()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00179">init_db()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00196">is_valid()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00208">selected_subdev()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00168">shutdown_daughterboards()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00157">~usrp_basic()</a>.</p>
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<a class="anchor" id="a686ea66e3f43c9ab6df60bd80f41ac3b"></a><!-- doxytag: member="usrp_basic::d_dbid" ref="a686ea66e3f43c9ab6df60bd80f41ac3b" args="[2]" -->
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<td class="memname">int <a class="el" href="classusrp__basic.html#a686ea66e3f43c9ab6df60bd80f41ac3b">usrp_basic::d_dbid</a>[2]<code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8h_source.html#l00965">usrp_basic_tx::daughterboard_id()</a>, <a class="el" href="usrp__basic_8h_source.html#l00850">usrp_basic_rx::daughterboard_id()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00179">init_db()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00986">usrp_basic_rx::probe_rx_slots()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01393">usrp_basic_tx::probe_tx_slots()</a>.</p>
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<a class="anchor" id="afa81d2ee842dd6eef04c422276f52d1d"></a><!-- doxytag: member="usrp_basic::d_fpga_master_clock_freq" ref="afa81d2ee842dd6eef04c422276f52d1d" args="" -->
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<td class="memname">long <a class="el" href="classusrp__basic.html#afa81d2ee842dd6eef04c422276f52d1d">usrp_basic::d_fpga_master_clock_freq</a><code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8h_source.html#l00183">fpga_master_clock_freq()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00192">set_fpga_master_clock_freq()</a>.</p>
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<a class="anchor" id="af3d08c8bcdd0ed116e76ffa5449004f2"></a><!-- doxytag: member="usrp_basic::d_fpga_shadows" ref="af3d08c8bcdd0ed116e76ffa5449004f2" args="[MAX_REGS]" -->
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<td class="memname">unsigned int <a class="el" href="classusrp__basic.html#af3d08c8bcdd0ed116e76ffa5449004f2">usrp_basic::d_fpga_shadows</a>[<a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">MAX_REGS</a>]<code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00394">_write_fpga_reg_masked()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00724">usrp_standard_rx::format()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00371">set_dc_offset_cl_enable()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00102">usrp_basic()</a>.</p>
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<a class="anchor" id="aad5f6f17a9fde484c67e7dbdd0491f74"></a><!-- doxytag: member="usrp_basic::d_udh" ref="aad5f6f17a9fde484c67e7dbdd0491f74" args="" -->
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<td class="memname"><a class="el" href="structusb__dev__handle.html">libusb_device_handle</a>* <a class="el" href="classusrp__basic.html#aad5f6f17a9fde484c67e7dbdd0491f74">usrp_basic::d_udh</a><code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00439">_read_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00242">_read_aux_adc()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00411">_read_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00461">_read_spi()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00476">_set_led()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00426">_write_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00236">_write_aux_dac()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00394">_write_fpga_reg_masked()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00454">_write_spi()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00986">usrp_basic_rx::probe_rx_slots()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01393">usrp_basic_tx::probe_tx_slots()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00923">usrp_basic_rx::read()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00264">read_eeprom()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00284">read_i2c()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00298">serial_number()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00961">usrp_basic_rx::set_rx_enable()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01367">usrp_basic_tx::set_tx_enable()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00102">usrp_basic()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00765">usrp_basic_rx::usrp_basic_rx()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01171">usrp_basic_tx::usrp_basic_tx()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00812">usrp_standard_tx::usrp_standard_tx()</a>, <a class="el" href="usrp__basic_8cc_source.html#l01323">usrp_basic_tx::write()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00258">write_eeprom()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00278">write_i2c()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00157">~usrp_basic()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00830">usrp_basic_rx::~usrp_basic_rx()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l01237">usrp_basic_tx::~usrp_basic_tx()</a>.</p>
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<a class="anchor" id="a4e5297f0010c8f39cfe4fff838b113a4"></a><!-- doxytag: member="usrp_basic::d_usb_data_rate" ref="a4e5297f0010c8f39cfe4fff838b113a4" args="" -->
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<td class="memname">int <a class="el" href="classusrp__basic.html#a4e5297f0010c8f39cfe4fff838b113a4">usrp_basic::d_usb_data_rate</a><code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00229">set_usb_data_rate()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00197">usb_data_rate()</a>.</p>
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<a class="anchor" id="a6d0fecbe64f35fef20293c27dc33a0b0"></a><!-- doxytag: member="usrp_basic::d_verbose" ref="a6d0fecbe64f35fef20293c27dc33a0b0" args="" -->
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<td class="memname">bool <a class="el" href="classusrp__basic.html#a6d0fecbe64f35fef20293c27dc33a0b0">usrp_basic::d_verbose</a><code> [protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00426">_write_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00394">_write_fpga_reg_masked()</a>, <a class="el" href="usrp__standard_8cc_source.html#l00650">usrp_standard_rx::set_rx_freq()</a>, <a class="el" href="usrp__standard_8cc_source.html#l01018">usrp_standard_tx::set_tx_freq()</a>, and <a class="el" href="usrp__basic_8h_source.html#l00199">set_verbose()</a>.</p>
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<a class="anchor" id="ae9277f41b745b1c96c422804fafd058a"></a><!-- doxytag: member="usrp_basic::MAX_REGS" ref="ae9277f41b745b1c96c422804fafd058a" args="" -->
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<td class="memname">const int <a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">usrp_basic::MAX_REGS</a> = 128<code> [static, protected]</code></td>
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<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00380">_write_fpga_reg()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00394">_write_fpga_reg_masked()</a>.</p>
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<a class="anchor" id="a364d3e56a0749a90cc5de2ac378e6863"></a><!-- doxytag: member="usrp_basic::READ_FAILED" ref="a364d3e56a0749a90cc5de2ac378e6863" args="" -->
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<td class="memname">const int <a class="el" href="classusrp__basic.html#a364d3e56a0749a90cc5de2ac378e6863">usrp_basic::READ_FAILED</a> = -99999<code> [static]</code></td>
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<p>magic value used on alternate register read interfaces </p>
<p>Referenced by <a class="el" href="usrp__basic_8cc_source.html#l00445">_read_9862()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00248">_read_aux_adc()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00417">_read_fpga_reg()</a>, <a class="el" href="usrp__basic_8cc_source.html#l00585">common_pga()</a>, and <a class="el" href="usrp__basic_8cc_source.html#l00681">common_read_io()</a>.</p>
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<hr/>The documentation for this class was generated from the following files:<ul>
<li><a class="el" href="usrp__basic_8h_source.html">usrp_basic.h</a></li>
<li><a class="el" href="usrp__basic_8cc.html">usrp_basic.cc</a></li>
</ul>
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<hr class="footer"/><address style="text-align: right;"><small>Generated on Wed Dec 29 19:44:43 2010 for Universal Software Radio Peripheral by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.3 </small></address>
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