--- VirtualBox-1.5.2_OSE/include/VBox/pdmdrv.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/pdmdrv.h 2007-12-03 12:07:19.000000000 +0100
@@ -221,35 +221,35 @@ typedef PDMDRVREG const *PCPDMDRVREG;
/** PDM Driver Classes.
* @{ */
/** Mouse input driver. */
-#define PDM_DRVREG_CLASS_MOUSE BIT(0)
+#define PDM_DRVREG_CLASS_MOUSE RT_BIT(0)
/** Keyboard input driver. */
-#define PDM_DRVREG_CLASS_KEYBOARD BIT(1)
+#define PDM_DRVREG_CLASS_KEYBOARD RT_BIT(1)
/** Display driver. */
-#define PDM_DRVREG_CLASS_DISPLAY BIT(2)
+#define PDM_DRVREG_CLASS_DISPLAY RT_BIT(2)
/** Network transport driver. */
-#define PDM_DRVREG_CLASS_NETWORK BIT(3)
+#define PDM_DRVREG_CLASS_NETWORK RT_BIT(3)
/** Block driver. */
-#define PDM_DRVREG_CLASS_BLOCK BIT(4)
+#define PDM_DRVREG_CLASS_BLOCK RT_BIT(4)
/** Media driver. */
-#define PDM_DRVREG_CLASS_MEDIA BIT(5)
+#define PDM_DRVREG_CLASS_MEDIA RT_BIT(5)
/** Mountable driver. */
-#define PDM_DRVREG_CLASS_MOUNTABLE BIT(6)
+#define PDM_DRVREG_CLASS_MOUNTABLE RT_BIT(6)
/** Audio driver. */
-#define PDM_DRVREG_CLASS_AUDIO BIT(7)
+#define PDM_DRVREG_CLASS_AUDIO RT_BIT(7)
/** VMMDev driver. */
-#define PDM_DRVREG_CLASS_VMMDEV BIT(8)
+#define PDM_DRVREG_CLASS_VMMDEV RT_BIT(8)
/** Status driver. */
-#define PDM_DRVREG_CLASS_STATUS BIT(9)
+#define PDM_DRVREG_CLASS_STATUS RT_BIT(9)
/** ACPI driver. */
-#define PDM_DRVREG_CLASS_ACPI BIT(10)
+#define PDM_DRVREG_CLASS_ACPI RT_BIT(10)
/** USB related driver. */
-#define PDM_DRVREG_CLASS_USB BIT(11)
+#define PDM_DRVREG_CLASS_USB RT_BIT(11)
/** ISCSI Transport related driver. */
-#define PDM_DRVREG_CLASS_ISCSITRANSPORT BIT(12)
+#define PDM_DRVREG_CLASS_ISCSITRANSPORT RT_BIT(12)
/** Char driver. */
-#define PDM_DRVREG_CLASS_CHAR BIT(13)
+#define PDM_DRVREG_CLASS_CHAR RT_BIT(13)
/** Stream driver. */
-#define PDM_DRVREG_CLASS_STREAM BIT(14)
+#define PDM_DRVREG_CLASS_STREAM RT_BIT(14)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/pdmdev.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/pdmdev.h 2007-12-03 12:07:19.000000000 +0100
@@ -331,43 +331,43 @@ typedef PDMDEVREG const *PCPDMDEVREG;
* The order is important, lower bit earlier instantiation.
* @{ */
/** Architecture device. */
-#define PDM_DEVREG_CLASS_ARCH BIT(0)
+#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
/** Architecture BIOS device. */
-#define PDM_DEVREG_CLASS_ARCH_BIOS BIT(1)
+#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
/** PCI bus brigde. */
-#define PDM_DEVREG_CLASS_BUS_PCI BIT(2)
+#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
/** ISA bus brigde. */
-#define PDM_DEVREG_CLASS_BUS_ISA BIT(3)
+#define PDM_DEVREG_CLASS_BUS_ISA RT_BIT(3)
/** Input device (mouse, keyboard, joystick,..). */
-#define PDM_DEVREG_CLASS_INPUT BIT(4)
+#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
/** Interrupt controller (PIC). */
-#define PDM_DEVREG_CLASS_PIC BIT(5)
+#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
/** Interval controoler (PIT). */
-#define PDM_DEVREG_CLASS_PIT BIT(6)
+#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
/** RTC/CMOS. */
-#define PDM_DEVREG_CLASS_RTC BIT(7)
+#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
/** DMA controller. */
-#define PDM_DEVREG_CLASS_DMA BIT(8)
+#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
/** VMM Device. */
-#define PDM_DEVREG_CLASS_VMM_DEV BIT(9)
+#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
/** Graphics device, like VGA. */
-#define PDM_DEVREG_CLASS_GRAPHICS BIT(10)
+#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
/** Storage controller device. */
-#define PDM_DEVREG_CLASS_STORAGE BIT(11)
+#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
/** Network interface controller. */
-#define PDM_DEVREG_CLASS_NETWORK BIT(12)
+#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
/** Audio. */
-#define PDM_DEVREG_CLASS_AUDIO BIT(13)
+#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
/** USB HIC. */
-#define PDM_DEVREG_CLASS_BUS_USB BIT(14)
+#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
/** ACPI. */
-#define PDM_DEVREG_CLASS_ACPI BIT(15)
+#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
/** Serial controller device. */
-#define PDM_DEVREG_CLASS_SERIAL BIT(16)
+#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
/** Parallel controller device */
-#define PDM_DEVREG_CLASS_PARALLEL BIT(17)
+#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
/** Misc devices (always last). */
-#define PDM_DEVREG_CLASS_MISC BIT(31)
+#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
/** @} */
@@ -375,11 +375,11 @@ typedef PDMDEVREG const *PCPDMDEVREG;
* @{
*/
/** Assert the IRQ (can assume value 1). */
-#define PDM_IRQ_LEVEL_HIGH BIT(0)
+#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
/** Deassert the IRQ (can assume value 0). */
#define PDM_IRQ_LEVEL_LOW 0
/** flip-flop - assert and then deassert it again immediately. */
-#define PDM_IRQ_LEVEL_FLIP_FLOP (BIT(1) | PDM_IRQ_LEVEL_HIGH)
+#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) | PDM_IRQ_LEVEL_HIGH)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/VBoxGuest.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/VBoxGuest.h 2007-12-03 12:07:19.000000000 +0100
@@ -77,13 +77,13 @@ typedef uint32_t vmmDevHypPhys;
*/
/** guest can (== wants to) handle absolute coordinates */
-#define VBOXGUEST_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
+#define VBOXGUEST_MOUSE_GUEST_CAN_ABSOLUTE RT_BIT(0)
/** host can (== wants to) send absolute coordinates */
-#define VBOXGUEST_MOUSE_HOST_CAN_ABSOLUTE BIT(1)
+#define VBOXGUEST_MOUSE_HOST_CAN_ABSOLUTE RT_BIT(1)
/** guest can *NOT* switch to software cursor and therefore depends on the host cursor */
-#define VBOXGUEST_MOUSE_GUEST_NEEDS_HOST_CURSOR BIT(2)
+#define VBOXGUEST_MOUSE_GUEST_NEEDS_HOST_CURSOR RT_BIT(2)
/** host does NOT provide support for drawing the cursor itself (e.g. L4 console) */
-#define VBOXGUEST_MOUSE_HOST_CANNOT_HWPOINTER BIT(3)
+#define VBOXGUEST_MOUSE_HOST_CANNOT_HWPOINTER RT_BIT(3)
/** fictive start address of the hypervisor physical memory for MmMapIoSpace */
#define HYPERVISOR_PHYSICAL_START 0xf8000000
@@ -915,17 +915,17 @@ typedef struct
*/
/** Host mouse capabilities has been changed. */
-#define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
+#define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED RT_BIT(0)
/** HGCM event. */
-#define VMMDEV_EVENT_HGCM BIT(1)
+#define VMMDEV_EVENT_HGCM RT_BIT(1)
/** A display change request has been issued. */
-#define VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST BIT(2)
+#define VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST RT_BIT(2)
/** Credentials are available for judgement. */
-#define VMMDEV_EVENT_JUDGE_CREDENTIALS BIT(3)
+#define VMMDEV_EVENT_JUDGE_CREDENTIALS RT_BIT(3)
/** The guest has been restored. */
-#define VMMDEV_EVENT_RESTORED BIT(4)
+#define VMMDEV_EVENT_RESTORED RT_BIT(4)
/** Seamless mode state changed */
-#define VMMDEV_EVENT_SEAMLESS_MODE_CHANGE_REQUEST BIT(5)
+#define VMMDEV_EVENT_SEAMLESS_MODE_CHANGE_REQUEST RT_BIT(5)
/** @} */
@@ -1144,26 +1144,26 @@ typedef struct _VBoxGuestHGCMCallInfo
#define VMMDEV_CREDENTIALS_STRLEN 128
/** query from host whether credentials are present */
-#define VMMDEV_CREDENTIALS_QUERYPRESENCE BIT(1)
+#define VMMDEV_CREDENTIALS_QUERYPRESENCE RT_BIT(1)
/** read credentials from host (can be combined with clear) */
-#define VMMDEV_CREDENTIALS_READ BIT(2)
+#define VMMDEV_CREDENTIALS_READ RT_BIT(2)
/** clear credentials on host (can be combined with read) */
-#define VMMDEV_CREDENTIALS_CLEAR BIT(3)
+#define VMMDEV_CREDENTIALS_CLEAR RT_BIT(3)
/** read credentials for judgement in the guest */
-#define VMMDEV_CREDENTIALS_READJUDGE BIT(8)
+#define VMMDEV_CREDENTIALS_READJUDGE RT_BIT(8)
/** clear credentials for judegement on the host */
-#define VMMDEV_CREDENTIALS_CLEARJUDGE BIT(9)
+#define VMMDEV_CREDENTIALS_CLEARJUDGE RT_BIT(9)
/** report credentials acceptance by guest */
-#define VMMDEV_CREDENTIALS_JUDGE_OK BIT(10)
+#define VMMDEV_CREDENTIALS_JUDGE_OK RT_BIT(10)
/** report credentials denial by guest */
-#define VMMDEV_CREDENTIALS_JUDGE_DENY BIT(11)
+#define VMMDEV_CREDENTIALS_JUDGE_DENY RT_BIT(11)
/** report that no judgement could be made by guest */
-#define VMMDEV_CREDENTIALS_JUDGE_NOJUDGEMENT BIT(12)
+#define VMMDEV_CREDENTIALS_JUDGE_NOJUDGEMENT RT_BIT(12)
/** flag telling the guest that credentials are present */
-#define VMMDEV_CREDENTIALS_PRESENT BIT(16)
+#define VMMDEV_CREDENTIALS_PRESENT RT_BIT(16)
/** flag telling guest that local logons should be prohibited */
-#define VMMDEV_CREDENTIALS_NOLOCALLOGON BIT(17)
+#define VMMDEV_CREDENTIALS_NOLOCALLOGON RT_BIT(17)
/** credentials request structure */
#pragma pack(4)
--- VirtualBox-1.5.2_OSE/include/VBox/hwacc_vmx.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/hwacc_vmx.h 2007-12-03 12:07:19.000000000 +0100
@@ -321,9 +321,9 @@
* @{
*/
/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT BIT(0)
+#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT BIT(3)
+#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
/** @} */
@@ -332,37 +332,37 @@
* @{
*/
/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT BIT(2)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
/* Use timestamp counter offset. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET BIT(3)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
/* VM Exit when executing the HLT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT BIT(7)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
/* VM Exit when executing the INVLPG instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT BIT(9)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
/* VM Exit when executing the MWAIT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT BIT(10)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
/* VM Exit when executing the RDPMC instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT BIT(11)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
/* VM Exit when executing the RDTSC instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT BIT(12)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
/* VM Exit on CR8 loads. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT BIT(19)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
/* VM Exit on CR8 stores. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT BIT(20)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
/* Use TPR shadow. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW BIT(21)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
/* VM Exit when executing a MOV DRx instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT BIT(23)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
/* VM Exit when executing IO instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT BIT(24)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
/* Use IO bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS BIT(25)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
/* Use MSR bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS BIT(28)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
/* VM Exit when executing the MONITOR instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT BIT(29)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
/* VM Exit when executing the PAUSE instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT BIT(30)
+#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
/** @} */
@@ -370,11 +370,11 @@
* @{
*/
/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE BIT(9)
+#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
/** In SMM mode after VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM BIT(10)
+#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON BIT(11)
+#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
/** @} */
@@ -382,9 +382,9 @@
* @{
*/
/** Return to long mode after a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 BIT(9)
+#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ BIT(15)
+#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
/** @} */
/** 32 Bits read-only fields
@@ -406,13 +406,13 @@
#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
-#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID BIT(11)
+#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
-#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & BIT(12))
+#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
-#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & BIT(31))
+#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
-#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~BIT(12))
+#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
/** @} */
/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
@@ -470,10 +470,10 @@
/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
* @{
*/
-#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI BIT(0)
-#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS BIT(1)
-#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI BIT(2)
-#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI BIT(3)
+#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
+#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
+#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
+#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
/** @} */
@@ -635,17 +635,17 @@
* @{
*/
/* Hardware breakpoint 0 was met. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 BIT(0)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
/* Hardware breakpoint 1 was met. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 BIT(1)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
/* Hardware breakpoint 2 was met. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 BIT(2)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
/* Hardware breakpoint 3 was met. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 BIT(3)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
/* At least one data or IO breakpoint was hit. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED BIT(12)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
/* A debug exception would have been triggered by single-step execution mode. */
-#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS BIT(14)
+#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
/* Bits 4-11, 13 and 15-63 are reserved. */
--- VirtualBox-1.5.2_OSE/include/VBox/cpum.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/cpum.h 2007-12-03 12:07:19.000000000 +0100
@@ -592,17 +592,17 @@ CPUMDECL(int) CPUMRestoreHostFPUState(PV
* to clear them is REM!
* @{
*/
-#define CPUM_CHANGED_FPU_REM BIT(0)
-#define CPUM_CHANGED_CR0 BIT(1)
-#define CPUM_CHANGED_CR4 BIT(2)
-#define CPUM_CHANGED_GLOBAL_TLB_FLUSH BIT(3)
-#define CPUM_CHANGED_CR3 BIT(4)
-#define CPUM_CHANGED_GDTR BIT(5)
-#define CPUM_CHANGED_IDTR BIT(6)
-#define CPUM_CHANGED_LDTR BIT(7)
-#define CPUM_CHANGED_TR BIT(8)
-#define CPUM_CHANGED_SYSENTER_MSR BIT(9)
-#define CPUM_CHANGED_HIDDEN_SEL_REGS BIT(10)
+#define CPUM_CHANGED_FPU_REM RT_BIT(0)
+#define CPUM_CHANGED_CR0 RT_BIT(1)
+#define CPUM_CHANGED_CR4 RT_BIT(2)
+#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
+#define CPUM_CHANGED_CR3 RT_BIT(4)
+#define CPUM_CHANGED_GDTR RT_BIT(5)
+#define CPUM_CHANGED_IDTR RT_BIT(6)
+#define CPUM_CHANGED_LDTR RT_BIT(7)
+#define CPUM_CHANGED_TR RT_BIT(8)
+#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
+#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
/** @} */
/**
--- VirtualBox-1.5.2_OSE/include/VBox/mm.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/mm.h 2007-12-03 12:07:19.000000000 +0100
@@ -46,7 +46,7 @@ __BEGIN_DECLS
* @remarks The current implementation will always reserve backing
* memory for reserved ranges to simplify things.
*/
-#define MM_RAM_FLAGS_RESERVED BIT(0)
+#define MM_RAM_FLAGS_RESERVED RT_BIT(0)
/** ROM - Read Only Memory.
* The page have a HC physical address which contains the BIOS code. All write
* access is trapped and ignored.
@@ -54,35 +54,35 @@ __BEGIN_DECLS
* HACK: Writable shadow ROM is indicated by both ROM and MMIO2 being
* set. (We're out of bits.)
*/
-#define MM_RAM_FLAGS_ROM BIT(1)
+#define MM_RAM_FLAGS_ROM RT_BIT(1)
/** MMIO - Memory Mapped I/O.
* All access is trapped and emulated. No physical backing is required, but
* might for various reasons be present.
*/
-#define MM_RAM_FLAGS_MMIO BIT(2)
+#define MM_RAM_FLAGS_MMIO RT_BIT(2)
/** MMIO2 - Memory Mapped I/O, variation 2.
* The virtualization is performed using real memory and only catching
* a few accesses for like keeping track for dirty pages.
* @remark Involved in the shadow ROM hack.
*/
-#define MM_RAM_FLAGS_MMIO2 BIT(3)
+#define MM_RAM_FLAGS_MMIO2 RT_BIT(3)
/** PGM has virtual page access handler(s) defined for pages with this flag. */
-#define MM_RAM_FLAGS_VIRTUAL_HANDLER BIT(4)
+#define MM_RAM_FLAGS_VIRTUAL_HANDLER RT_BIT(4)
/** PGM has virtual page access handler(s) for write access. */
-#define MM_RAM_FLAGS_VIRTUAL_WRITE BIT(5)
+#define MM_RAM_FLAGS_VIRTUAL_WRITE RT_BIT(5)
/** PGM has virtual page access handler(s) for all access. */
-#define MM_RAM_FLAGS_VIRTUAL_ALL BIT(6)
+#define MM_RAM_FLAGS_VIRTUAL_ALL RT_BIT(6)
/** PGM has physical page access handler(s) defined for pages with this flag. */
-#define MM_RAM_FLAGS_PHYSICAL_HANDLER BIT(7)
+#define MM_RAM_FLAGS_PHYSICAL_HANDLER RT_BIT(7)
/** PGM has physical page access handler(s) for write access. */
-#define MM_RAM_FLAGS_PHYSICAL_WRITE BIT(8)
+#define MM_RAM_FLAGS_PHYSICAL_WRITE RT_BIT(8)
/** PGM has physical page access handler(s) for all access. */
-#define MM_RAM_FLAGS_PHYSICAL_ALL BIT(9)
+#define MM_RAM_FLAGS_PHYSICAL_ALL RT_BIT(9)
/** PGM has physical page access handler(s) for this page and has temporarily disabled it. */
-#define MM_RAM_FLAGS_PHYSICAL_TEMP_OFF BIT(10)
+#define MM_RAM_FLAGS_PHYSICAL_TEMP_OFF RT_BIT(10)
/** Physical backing memory is allocated dynamically. Not set implies a one time static allocation. */
-#define MM_RAM_FLAGS_DYNAMIC_ALLOC BIT(11)
+#define MM_RAM_FLAGS_DYNAMIC_ALLOC RT_BIT(11)
/** The shift used to get the reference count. */
#define MM_RAM_FLAGS_CREFS_SHIFT 62
--- VirtualBox-1.5.2_OSE/include/VBox/pdmifs.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/pdmifs.h 2007-12-03 12:07:19.000000000 +0100
@@ -189,9 +189,9 @@ typedef struct PDMIMOUSEPORT
/** Mouse button defines for PDMIMOUSEPORT::pfnPutEvent.
* @{ */
-#define PDMIMOUSEPORT_BUTTON_LEFT BIT(0)
-#define PDMIMOUSEPORT_BUTTON_RIGHT BIT(1)
-#define PDMIMOUSEPORT_BUTTON_MIDDLE BIT(2)
+#define PDMIMOUSEPORT_BUTTON_LEFT RT_BIT(0)
+#define PDMIMOUSEPORT_BUTTON_RIGHT RT_BIT(1)
+#define PDMIMOUSEPORT_BUTTON_MIDDLE RT_BIT(2)
/** @} */
@@ -1809,13 +1809,13 @@ typedef union PDMLEDCORE
/** LED bit masks for the u32 view.
* @{ */
/** Reading/Receiving indicator. */
-#define PDMLED_READING BIT(0)
+#define PDMLED_READING RT_BIT(0)
/** Writing/Sending indicator. */
-#define PDMLED_WRITING BIT(1)
+#define PDMLED_WRITING RT_BIT(1)
/** Busy indicator. */
-#define PDMLED_BUSY BIT(2)
+#define PDMLED_BUSY RT_BIT(2)
/** Error indicator. */
-#define PDMLED_ERROR BIT(3)
+#define PDMLED_ERROR RT_BIT(3)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/vusb.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/vusb.h 2007-12-03 12:07:19.000000000 +0100
@@ -32,9 +32,9 @@ __BEGIN_DECLS
/** @name USB Standard version flags.
* @{ */
/** Indicates USB 1.1 support. */
-#define VUSB_STDVER_11 BIT(1)
+#define VUSB_STDVER_11 RT_BIT(1)
/** Indicates USB 2.0 support. */
-#define VUSB_STDVER_20 BIT(2)
+#define VUSB_STDVER_20 RT_BIT(2)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/hwacc_svm.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/hwacc_svm.h 2007-12-03 12:07:19.000000000 +0100
@@ -229,69 +229,69 @@
* @{
*/
/* 0 Intercept INTR (physical maskable interrupt) */
-#define SVM_CTRL1_INTERCEPT_INTR BIT(0)
+#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
/* 1 Intercept NMI */
-#define SVM_CTRL1_INTERCEPT_NMI BIT(1)
+#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
/* 2 Intercept SMI */
-#define SVM_CTRL1_INTERCEPT_SMI BIT(2)
+#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
/* 3 Intercept INIT */
-#define SVM_CTRL1_INTERCEPT_INIT BIT(3)
+#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
/* 4 Intercept VINTR (virtual maskable interrupt) */
-#define SVM_CTRL1_INTERCEPT_VINTR BIT(4)
+#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
-#define SVM_CTRL1_INTERCEPT_CR0 BIT(5)
+#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
/* 6 Intercept reads of IDTR */
-#define SVM_CTRL1_INTERCEPT_IDTR_READS BIT(6)
+#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
/* 7 Intercept reads of GDTR */
-#define SVM_CTRL1_INTERCEPT_GDTR_READS BIT(7)
+#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
/* 8 Intercept reads of LDTR */
-#define SVM_CTRL1_INTERCEPT_LDTR_READS BIT(8)
+#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
/* 9 Intercept reads of TR */
-#define SVM_CTRL1_INTERCEPT_TR_READS BIT(9)
+#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
/* 10 Intercept writes of IDTR */
-#define SVM_CTRL1_INTERCEPT_IDTR_WRITES BIT(10)
+#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
/* 11 Intercept writes of GDTR */
-#define SVM_CTRL1_INTERCEPT_GDTR_WRITES BIT(11)
+#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
/* 12 Intercept writes of LDTR */
-#define SVM_CTRL1_INTERCEPT_LDTR_WRITES BIT(12)
+#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
/* 13 Intercept writes of TR */
-#define SVM_CTRL1_INTERCEPT_TR_WRITES BIT(13)
+#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
/* 14 Intercept RDTSC instruction */
-#define SVM_CTRL1_INTERCEPT_RDTSC BIT(14)
+#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
/* 15 Intercept RDPMC instruction */
-#define SVM_CTRL1_INTERCEPT_RDPMC BIT(15)
+#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
/* 16 Intercept PUSHF instruction */
-#define SVM_CTRL1_INTERCEPT_PUSHF BIT(16)
+#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
/* 17 Intercept POPF instruction */
-#define SVM_CTRL1_INTERCEPT_POPF BIT(17)
+#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
/* 18 Intercept CPUID instruction */
-#define SVM_CTRL1_INTERCEPT_CPUID BIT(18)
+#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
/* 19 Intercept RSM instruction */
-#define SVM_CTRL1_INTERCEPT_RSM BIT(19)
+#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
/* 20 Intercept IRET instruction */
-#define SVM_CTRL1_INTERCEPT_IRET BIT(20)
+#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
/* 21 Intercept INTn instruction */
-#define SVM_CTRL1_INTERCEPT_INTN BIT(21)
+#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
/* 22 Intercept INVD instruction */
-#define SVM_CTRL1_INTERCEPT_INVD BIT(22)
+#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
/* 23 Intercept PAUSE instruction */
-#define SVM_CTRL1_INTERCEPT_PAUSE BIT(23)
+#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
/* 24 Intercept HLT instruction */
-#define SVM_CTRL1_INTERCEPT_HLT BIT(24)
+#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
/* 25 Intercept INVLPG instruction */
-#define SVM_CTRL1_INTERCEPT_INVLPG BIT(25)
+#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
/* 26 Intercept INVLPGA instruction */
-#define SVM_CTRL1_INTERCEPT_INVLPGA BIT(26)
+#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
-#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP BIT(27)
+#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
-#define SVM_CTRL1_INTERCEPT_MSR_SHADOW BIT(28)
+#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
/* 29 Intercept task switches. */
-#define SVM_CTRL1_INTERCEPT_TASK_SWITCH BIT(29)
+#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
-#define SVM_CTRL1_INTERCEPT_FERR_FREEZE BIT(30)
+#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
/* 31 Intercept shutdown events. */
-#define SVM_CTRL1_INTERCEPT_SHUTDOWN BIT(31)
+#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
/** @} */
@@ -299,37 +299,37 @@
* @{
*/
/* 0 Intercept VMRUN instruction */
-#define SVM_CTRL2_INTERCEPT_VMRUN BIT(0)
+#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
/* 1 Intercept VMMCALL instruction */
-#define SVM_CTRL2_INTERCEPT_VMMCALL BIT(1)
+#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
/* 2 Intercept VMLOAD instruction */
-#define SVM_CTRL2_INTERCEPT_VMLOAD BIT(2)
+#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
/* 3 Intercept VMSAVE instruction */
-#define SVM_CTRL2_INTERCEPT_VMSAVE BIT(3)
+#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
/* 4 Intercept STGI instruction */
-#define SVM_CTRL2_INTERCEPT_STGI BIT(4)
+#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
/* 5 Intercept CLGI instruction */
-#define SVM_CTRL2_INTERCEPT_CLGI BIT(5)
+#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
/* 6 Intercept SKINIT instruction */
-#define SVM_CTRL2_INTERCEPT_SKINIT BIT(6)
+#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
/* 7 Intercept RDTSCP instruction */
-#define SVM_CTRL2_INTERCEPT_RDTSCP BIT(7)
+#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
/* 8 Intercept ICEBP instruction */
-#define SVM_CTRL2_INTERCEPT_ICEBP BIT(8)
+#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
/* 9 Intercept WBINVD instruction */
-#define SVM_CTRL2_INTERCEPT_WBINVD BIT(9)
+#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
/** @} */
/** @name SVM_VMCB.ctrl.u64NestedPaging
* @{
*/
-#define SVM_NESTED_PAGING_ENABLE BIT(0)
+#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
/** @} */
/** @name SVM_VMCB.ctrl.u64IntShadow
* @{
*/
-#define SVM_INTERRUPT_SHADOW_ACTIVE BIT(0)
+#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/selm.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/selm.h 2007-12-03 12:07:19.000000000 +0100
@@ -147,9 +147,9 @@ SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, X8
/** Flags for SELMToFlatEx().
* @{ */
/** Don't check the RPL,DPL or CPL. */
-#define SELMTOFLAT_FLAGS_NO_PL BIT(8)
+#define SELMTOFLAT_FLAGS_NO_PL RT_BIT(8)
/** Flags contains CPL information. */
-#define SELMTOFLAT_FLAGS_HAVE_CPL BIT(9)
+#define SELMTOFLAT_FLAGS_HAVE_CPL RT_BIT(9)
/** CPL is 3. */
#define SELMTOFLAT_FLAGS_CPL3 3
/** CPL is 2. */
@@ -161,7 +161,7 @@ SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, X8
/** Get the CPL from the flags. */
#define SELMTOFLAT_FLAGS_CPL(fFlags) ((fFlags) & X86_SEL_RPL)
/** Allow converting using Hypervisor GDT entries. */
-#define SELMTOFLAT_FLAGS_HYPER BIT(10)
+#define SELMTOFLAT_FLAGS_HYPER RT_BIT(10)
/** @} */
/**
--- VirtualBox-1.5.2_OSE/include/VBox/VBoxGuest16.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/VBoxGuest16.h 2007-12-03 12:07:19.000000000 +0100
@@ -12,7 +12,7 @@
#ifndef ___VBox_VBoxGuest16_h
#define ___VBox_VBoxGuest16_h
-#define BIT(bit) (1UL << (bit))
+#define RT_BIT(bit) (1UL << (bit))
#define VMMDEV_VERSION 0x00010004UL
@@ -36,11 +36,11 @@ typedef VBGOS2IDC *PVBGOS2IDC;
#define VBOXGUEST_IOCTL_OS2_IDC_DISCONNECT 48
-#define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
-#define VMMDEV_EVENT_HGCM BIT(1)
-#define VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST BIT(2)
-#define VMMDEV_EVENT_JUDGE_CREDENTIALS BIT(3)
-#define VMMDEV_EVENT_RESTORED BIT(4)
+#define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED RT_BIT(0)
+#define VMMDEV_EVENT_HGCM RT_BIT(1)
+#define VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST RT_BIT(2)
+#define VMMDEV_EVENT_JUDGE_CREDENTIALS RT_BIT(3)
+#define VMMDEV_EVENT_RESTORED RT_BIT(4)
#define VBOXGUEST_WAITEVENT_OK 0
@@ -72,10 +72,10 @@ typedef struct
#define VMMDevReq_SetMouseStatus 2
#define VMMDevReq_CtlGuestFilterMask 42
-#define VBOXGUEST_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
-#define VBOXGUEST_MOUSE_HOST_CAN_ABSOLUTE BIT(1)
-#define VBOXGUEST_MOUSE_GUEST_NEEDS_HOST_CURSOR BIT(2)
-#define VBOXGUEST_MOUSE_HOST_CANNOT_HWPOINTER BIT(3)
+#define VBOXGUEST_MOUSE_GUEST_CAN_ABSOLUTE RT_BIT(0)
+#define VBOXGUEST_MOUSE_HOST_CAN_ABSOLUTE RT_BIT(1)
+#define VBOXGUEST_MOUSE_GUEST_NEEDS_HOST_CURSOR RT_BIT(2)
+#define VBOXGUEST_MOUSE_HOST_CANNOT_HWPOINTER RT_BIT(3)
typedef struct
{
--- VirtualBox-1.5.2_OSE/include/VBox/dbg.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/dbg.h 2007-12-03 12:07:19.000000000 +0100
@@ -152,7 +152,7 @@ typedef const DBGCVARDESC *PCDBGCVARDESC
/** Variable descriptor flags.
* @{ */
/** Indicates that the variable depends on the previous being present. */
-#define DBGCVD_FLAGS_DEP_PREV BIT(1)
+#define DBGCVD_FLAGS_DEP_PREV RT_BIT(1)
/** @} */
--- VirtualBox-1.5.2_OSE/include/VBox/dbgf.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/dbgf.h 2007-12-03 12:07:19.000000000 +0100
@@ -134,11 +134,11 @@ typedef const DBGFADDRESS *PCDBGFADDRESS
#define DBGFADDRESS_FLAGS_TYPE_MASK 3
/** Set if the address is valid. */
-#define DBGFADDRESS_FLAGS_VALID BIT(2)
+#define DBGFADDRESS_FLAGS_VALID RT_BIT(2)
/** The address is within the hypervisor memoary area (HMA).
* If not set, the address can be assumed to be a guest address. */
-#define DBGFADDRESS_FLAGS_HMA BIT(3)
+#define DBGFADDRESS_FLAGS_HMA RT_BIT(3)
/** Checks if the mixed address is flat or not. */
#define DBGFADDRESS_IS_FLAT(pAddress) ( ((pAddress)->fFlags & DBGFADDRESS_FLAGS_TYPE_MASK) == DBGFADDRESS_FLAGS_FLAT )
@@ -832,7 +832,7 @@ typedef FNDBGFHANDLEREXT *PFNDBGFHANDLE
/** @name Flags for the info registration functions.
* @{ */
/** The handler must run on the EMT. */
-#define DBGFINFO_FLAGS_RUN_ON_EMT BIT(0)
+#define DBGFINFO_FLAGS_RUN_ON_EMT RT_BIT(0)
/** @} */
@@ -1320,14 +1320,14 @@ typedef struct DBGFSTACKFRAME
* @{ */
/** Set if the content of the frame is filled in by DBGFR3StackWalk() and can be used
* to construct the next frame. */
-#define DBGFSTACKFRAME_FLAGS_ALL_VALID BIT(0)
+#define DBGFSTACKFRAME_FLAGS_ALL_VALID RT_BIT(0)
/** This is the last stack frame we can read.
* This flag is not set if the walk stop because of max dept or recursion. */
-#define DBGFSTACKFRAME_FLAGS_LAST BIT(1)
+#define DBGFSTACKFRAME_FLAGS_LAST RT_BIT(1)
/** This is the last record because we detected a loop. */
-#define DBGFSTACKFRAME_FLAGS_LOOP BIT(2)
+#define DBGFSTACKFRAME_FLAGS_LOOP RT_BIT(2)
/** This is the last record because we reached the maximum depth. */
-#define DBGFSTACKFRAME_FLAGS_MAX_DEPTH BIT(3)
+#define DBGFSTACKFRAME_FLAGS_MAX_DEPTH RT_BIT(3)
/** @} */
/**
@@ -1391,17 +1391,17 @@ DBGFR3DECL(void) DBGFR3StackWalkEnd(PVM
/** Flags to pass to DBGFR3DisasInstrEx().
* @{ */
/** Disassemble the current guest instruction, with annotations. */
-#define DBGF_DISAS_FLAGS_CURRENT_GUEST BIT(0)
+#define DBGF_DISAS_FLAGS_CURRENT_GUEST RT_BIT(0)
/** Disassemble the current hypervisor instruction, with annotations. */
-#define DBGF_DISAS_FLAGS_CURRENT_HYPER BIT(1)
+#define DBGF_DISAS_FLAGS_CURRENT_HYPER RT_BIT(1)
/** No annotations for current context. */
-#define DBGF_DISAS_FLAGS_NO_ANNOTATION BIT(2)
+#define DBGF_DISAS_FLAGS_NO_ANNOTATION RT_BIT(2)
/** No symbol lookup. */
-#define DBGF_DISAS_FLAGS_NO_SYMBOLS BIT(3)
+#define DBGF_DISAS_FLAGS_NO_SYMBOLS RT_BIT(3)
/** No instruction bytes. */
-#define DBGF_DISAS_FLAGS_NO_BYTES BIT(4)
+#define DBGF_DISAS_FLAGS_NO_BYTES RT_BIT(4)
/** No address in the output. */
-#define DBGF_DISAS_FLAGS_NO_ADDRESS BIT(5)
+#define DBGF_DISAS_FLAGS_NO_ADDRESS RT_BIT(5)
/** @} */
/** Special flat selector. */
--- VirtualBox-1.5.2_OSE/include/VBox/x86.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/x86.h 2007-12-03 12:07:19.000000000 +0100
@@ -115,39 +115,39 @@ typedef const X86EFLAGS *PCX86EFLAGS;
* @{
*/
/** Bit 0 - CF - Carry flag - Status flag. */
-#define X86_EFL_CF BIT(0)
+#define X86_EFL_CF RT_BIT(0)
/** Bit 2 - PF - Parity flag - Status flag. */
-#define X86_EFL_PF BIT(2)
+#define X86_EFL_PF RT_BIT(2)
/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
-#define X86_EFL_AF BIT(4)
+#define X86_EFL_AF RT_BIT(4)
/** Bit 6 - ZF - Zero flag - Status flag. */
-#define X86_EFL_ZF BIT(6)
+#define X86_EFL_ZF RT_BIT(6)
/** Bit 7 - SF - Signed flag - Status flag. */
-#define X86_EFL_SF BIT(7)
+#define X86_EFL_SF RT_BIT(7)
/** Bit 8 - TF - Trap flag - System flag. */
-#define X86_EFL_TF BIT(8)
+#define X86_EFL_TF RT_BIT(8)
/** Bit 9 - IF - Interrupt flag - System flag. */
-#define X86_EFL_IF BIT(9)
+#define X86_EFL_IF RT_BIT(9)
/** Bit 10 - DF - Direction flag - Control flag. */
-#define X86_EFL_DF BIT(10)
+#define X86_EFL_DF RT_BIT(10)
/** Bit 11 - OF - Overflow flag - Status flag. */
-#define X86_EFL_OF BIT(11)
+#define X86_EFL_OF RT_BIT(11)
/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
-#define X86_EFL_IOPL (BIT(12) | BIT(13))
+#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
/** Bit 14 - NT - Nested task flag - System flag. */
-#define X86_EFL_NT BIT(14)
+#define X86_EFL_NT RT_BIT(14)
/** Bit 16 - RF - Resume flag - System flag. */
-#define X86_EFL_RF BIT(16)
+#define X86_EFL_RF RT_BIT(16)
/** Bit 17 - VM - Virtual 8086 mode - System flag. */
-#define X86_EFL_VM BIT(17)
+#define X86_EFL_VM RT_BIT(17)
/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
-#define X86_EFL_AC BIT(18)
+#define X86_EFL_AC RT_BIT(18)
/** Bit 19 - VIF - Virtual interupt flag - System flag. */
-#define X86_EFL_VIF BIT(19)
+#define X86_EFL_VIF RT_BIT(19)
/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
-#define X86_EFL_VIP BIT(20)
+#define X86_EFL_VIP RT_BIT(20)
/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
-#define X86_EFL_ID BIT(21)
+#define X86_EFL_ID RT_BIT(21)
/** IOPL shift. */
#define X86_EFL_IOPL_SHIFT 12
/** The the IOPL level from the flags. */
@@ -290,87 +290,87 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
* @{
*/
/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
-#define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
+#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
-#define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
+#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
-#define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
+#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
/** ECX Bit 5 - VMX - Virtual Machine Technology. */
-#define X86_CPUID_FEATURE_ECX_VMX BIT(5)
+#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
-#define X86_CPUID_FEATURE_ECX_EST BIT(7)
+#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
-#define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
+#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
-#define X86_CPUID_FEATURE_ECX_SSSE3 BIT(9)
+#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
-#define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
+#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
/** ECX Bit 13 - CX16 - CMPXCHG16B. */
-#define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
+#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
-#define X86_CPUID_FEATURE_ECX_TPRUPDATE BIT(14)
+#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
/** ECX Bit 23 - POPCOUNT instruction. */
-#define X86_CPUID_FEATURE_ECX_POPCOUNT BIT(23)
+#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
/** Bit 0 - FPU - x87 FPU on Chip. */
-#define X86_CPUID_FEATURE_EDX_FPU BIT(0)
+#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
-#define X86_CPUID_FEATURE_EDX_VME BIT(1)
+#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
/** Bit 2 - DE - Debugging extensions. */
-#define X86_CPUID_FEATURE_EDX_DE BIT(2)
+#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
/** Bit 3 - PSE - Page Size Extension. */
-#define X86_CPUID_FEATURE_EDX_PSE BIT(3)
+#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
/** Bit 4 - TSC - Time Stamp Counter. */
-#define X86_CPUID_FEATURE_EDX_TSC BIT(4)
+#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
-#define X86_CPUID_FEATURE_EDX_MSR BIT(5)
+#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
/** Bit 6 - PAE - Physical Address Extension. */
-#define X86_CPUID_FEATURE_EDX_PAE BIT(6)
+#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
/** Bit 7 - MCE - Machine Check Exception. */
-#define X86_CPUID_FEATURE_EDX_MCE BIT(7)
+#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
-#define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
+#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
/** Bit 9 - APIC - APIC On-Chip. */
-#define X86_CPUID_FEATURE_EDX_APIC BIT(9)
+#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
-#define X86_CPUID_FEATURE_EDX_SEP BIT(11)
+#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
/** Bit 12 - MTRR - Memory Type Range Registers. */
-#define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
+#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
/** Bit 13 - PGE - PTE Global Bit. */
-#define X86_CPUID_FEATURE_EDX_PGE BIT(13)
+#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
/** Bit 14 - MCA - Machine Check Architecture. */
-#define X86_CPUID_FEATURE_EDX_MCA BIT(14)
+#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
/** Bit 15 - CMOV - Conditional Move Instructions. */
-#define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
+#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
/** Bit 16 - PAT - Page Attribute Table. */
-#define X86_CPUID_FEATURE_EDX_PAT BIT(16)
+#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
-#define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
+#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
/** Bit 18 - PSN - Processor Serial Number. */
-#define X86_CPUID_FEATURE_EDX_PSN BIT(18)
+#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
/** Bit 19 - CLFSH - CLFLUSH Instruction. */
-#define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
+#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
/** Bit 21 - DS - Debug Store. */
-#define X86_CPUID_FEATURE_EDX_DS BIT(21)
+#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
-#define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
+#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
/** Bit 23 - MMX - Intel MMX Technology. */
-#define X86_CPUID_FEATURE_EDX_MMX BIT(23)
+#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
-#define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
+#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
/** Bit 25 - SSE - SSE Support. */
-#define X86_CPUID_FEATURE_EDX_SSE BIT(25)
+#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
/** Bit 26 - SSE2 - SSE2 Support. */
-#define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
+#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
/** Bit 27 - SS - Self Snoop. */
-#define X86_CPUID_FEATURE_EDX_SS BIT(27)
+#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
/** Bit 28 - HTT - Hyper-Threading Technology. */
-#define X86_CPUID_FEATURE_EDX_HTT BIT(28)
+#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
/** Bit 29 - TM - Therm. Monitor. */
-#define X86_CPUID_FEATURE_EDX_TM BIT(29)
+#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
/** Bit 31 - PBE - Pending Break Enabled. */
-#define X86_CPUID_FEATURE_EDX_PBE BIT(31)
+#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
/** @} */
@@ -379,84 +379,84 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
* @{
*/
/** Bit 0 - FPU - x87 FPU on Chip. */
-#define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
+#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
-#define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
+#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
/** Bit 2 - DE - Debugging extensions. */
-#define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
+#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
/** Bit 3 - PSE - Page Size Extension. */
-#define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
+#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
/** Bit 4 - TSC - Time Stamp Counter. */
-#define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
+#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
-#define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
+#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
/** Bit 6 - PAE - Physical Address Extension. */
-#define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
+#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
/** Bit 7 - MCE - Machine Check Exception. */
-#define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
+#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
-#define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
+#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
/** Bit 9 - APIC - APIC On-Chip. */
-#define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
+#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
-#define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
+#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
/** Bit 12 - MTRR - Memory Type Range Registers. */
-#define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
+#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
/** Bit 13 - PGE - PTE Global Bit. */
-#define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
+#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
/** Bit 14 - MCA - Machine Check Architecture. */
-#define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
+#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
/** Bit 15 - CMOV - Conditional Move Instructions. */
-#define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
+#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
/** Bit 16 - PAT - Page Attribute Table. */
-#define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
+#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
-#define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
+#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
/** Bit 20 - NX - AMD No-Execute Page Protection. */
-#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
+#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
-#define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
+#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
/** Bit 23 - MMX - Intel MMX Technology. */
-#define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
+#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
-#define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
+#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
-#define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
+#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
-#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB BIT(26)
+#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
-#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP BIT(27)
+#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
/** Bit 29 - LM - AMD Long Mode. */
-#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
+#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
-#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
+#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
/** Bit 31 - 3DNOW - AMD 3DNow. */
-#define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
+#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
-#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF BIT(0)
+#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
/** Bit 1 - CMPL - Core multi-processing legacy mode. */
-#define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
+#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
/** Bit 2 - SVM - AMD VM extensions. */
-#define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
+#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
-#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC BIT(3)
+#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
-#define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
+#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
-#define X86_CPUID_AMD_FEATURE_ECX_ABM BIT(5)
+#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
-#define X86_CPUID_AMD_FEATURE_ECX_SSE4A BIT(6)
+#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
-#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE BIT(7)
+#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
-#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF BIT(8)
+#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
/** Bit 9 - OSVW - AMD OS visible workaround. */
-#define X86_CPUID_AMD_FEATURE_ECX_OSVW BIT(9)
+#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
-#define X86_CPUID_AMD_FEATURE_ECX_SKINIT BIT(12)
+#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
/** Bit 13 - WDT - AMD Watchdog timer support. */
-#define X86_CPUID_AMD_FEATURE_ECX_WDT BIT(13)
+#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
/** @} */
@@ -464,47 +464,47 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
/** @name CR0
* @{ */
/** Bit 0 - PE - Protection Enabled */
-#define X86_CR0_PE BIT(0)
-#define X86_CR0_PROTECTION_ENABLE BIT(0)
+#define X86_CR0_PE RT_BIT(0)
+#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
/** Bit 1 - MP - Monitor Coprocessor */
-#define X86_CR0_MP BIT(1)
-#define X86_CR0_MONITOR_COPROCESSOR BIT(1)
+#define X86_CR0_MP RT_BIT(1)
+#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
/** Bit 2 - EM - Emulation. */
-#define X86_CR0_EM BIT(2)
-#define X86_CR0_EMULATE_FPU BIT(2)
+#define X86_CR0_EM RT_BIT(2)
+#define X86_CR0_EMULATE_FPU RT_BIT(2)
/** Bit 3 - TS - Task Switch. */
-#define X86_CR0_TS BIT(3)
-#define X86_CR0_TASK_SWITCH BIT(3)
+#define X86_CR0_TS RT_BIT(3)
+#define X86_CR0_TASK_SWITCH RT_BIT(3)
/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
-#define X86_CR0_ET BIT(4)
-#define X86_CR0_EXTENSION_TYPE BIT(4)
+#define X86_CR0_ET RT_BIT(4)
+#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
/** Bit 5 - NE - Numeric error. */
-#define X86_CR0_NE BIT(5)
-#define X86_CR0_NUMERIC_ERROR BIT(5)
+#define X86_CR0_NE RT_BIT(5)
+#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
/** Bit 16 - WP - Write Protect. */
-#define X86_CR0_WP BIT(16)
-#define X86_CR0_WRITE_PROTECT BIT(16)
+#define X86_CR0_WP RT_BIT(16)
+#define X86_CR0_WRITE_PROTECT RT_BIT(16)
/** Bit 18 - AM - Alignment Mask. */
-#define X86_CR0_AM BIT(18)
-#define X86_CR0_ALIGMENT_MASK BIT(18)
+#define X86_CR0_AM RT_BIT(18)
+#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
/** Bit 29 - NW - Not Write-though. */
-#define X86_CR0_NW BIT(29)
-#define X86_CR0_NOT_WRITE_THROUGH BIT(29)
+#define X86_CR0_NW RT_BIT(29)
+#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
/** Bit 30 - WP - Cache Disable. */
-#define X86_CR0_CD BIT(30)
-#define X86_CR0_CACHE_DISABLE BIT(30)
+#define X86_CR0_CD RT_BIT(30)
+#define X86_CR0_CACHE_DISABLE RT_BIT(30)
/** Bit 31 - PG - Paging. */
-#define X86_CR0_PG BIT(31)
-#define X86_CR0_PAGING BIT(31)
+#define X86_CR0_PG RT_BIT(31)
+#define X86_CR0_PAGING RT_BIT(31)
/** @} */
/** @name CR3
* @{ */
/** Bit 3 - PWT - Page-level Writes Transparent. */
-#define X86_CR3_PWT BIT(3)
+#define X86_CR3_PWT RT_BIT(3)
/** Bit 4 - PCD - Page-level Cache Disable. */
-#define X86_CR3_PCD BIT(4)
+#define X86_CR3_PCD RT_BIT(4)
/** Bits 12-31 - - Page directory page number. */
#define X86_CR3_PAGE_MASK (0xfffff000)
/** Bits 5-31 - - PAE Page directory page number. */
@@ -515,77 +515,77 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
/** @name CR4
* @{ */
/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
-#define X86_CR4_VME BIT(0)
+#define X86_CR4_VME RT_BIT(0)
/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
-#define X86_CR4_PVI BIT(1)
+#define X86_CR4_PVI RT_BIT(1)
/** Bit 2 - TSD - Time Stamp Disable. */
-#define X86_CR4_TSD BIT(2)
+#define X86_CR4_TSD RT_BIT(2)
/** Bit 3 - DE - Debugging Extensions. */
-#define X86_CR4_DE BIT(3)
+#define X86_CR4_DE RT_BIT(3)
/** Bit 4 - PSE - Page Size Extension. */
-#define X86_CR4_PSE BIT(4)
+#define X86_CR4_PSE RT_BIT(4)
/** Bit 5 - PAE - Physical Address Extension. */
-#define X86_CR4_PAE BIT(5)
+#define X86_CR4_PAE RT_BIT(5)
/** Bit 6 - MCE - Machine-Check Enable. */
-#define X86_CR4_MCE BIT(6)
+#define X86_CR4_MCE RT_BIT(6)
/** Bit 7 - PGE - Page Global Enable. */
-#define X86_CR4_PGE BIT(7)
+#define X86_CR4_PGE RT_BIT(7)
/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
-#define X86_CR4_PCE BIT(8)
+#define X86_CR4_PCE RT_BIT(8)
/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
-#define X86_CR4_OSFSXR BIT(9)
+#define X86_CR4_OSFSXR RT_BIT(9)
/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
-#define X86_CR4_OSXMMEEXCPT BIT(10)
+#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
/** Bit 13 - VMXE - VMX mode is enabled. */
-#define X86_CR4_VMXE BIT(13)
+#define X86_CR4_VMXE RT_BIT(13)
/** @} */
/** @name DR6
* @{ */
/** Bit 0 - B0 - Breakpoint 0 condition detected. */
-#define X86_DR6_B0 BIT(0)
+#define X86_DR6_B0 RT_BIT(0)
/** Bit 1 - B1 - Breakpoint 1 condition detected. */
-#define X86_DR6_B1 BIT(1)
+#define X86_DR6_B1 RT_BIT(1)
/** Bit 2 - B2 - Breakpoint 2 condition detected. */
-#define X86_DR6_B2 BIT(2)
+#define X86_DR6_B2 RT_BIT(2)
/** Bit 3 - B3 - Breakpoint 3 condition detected. */
-#define X86_DR6_B3 BIT(3)
+#define X86_DR6_B3 RT_BIT(3)
/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
-#define X86_DR6_BD BIT(13)
+#define X86_DR6_BD RT_BIT(13)
/** Bit 14 - BS - Single step */
-#define X86_DR6_BS BIT(14)
+#define X86_DR6_BS RT_BIT(14)
/** Bit 15 - BT - Task switch. (TSS T bit.) */
-#define X86_DR6_BT BIT(15)
+#define X86_DR6_BT RT_BIT(15)
/** @} */
/** @name DR7
* @{ */
/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
-#define X86_DR7_L0 BIT(0)
+#define X86_DR7_L0 RT_BIT(0)
/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
-#define X86_DR7_G0 BIT(1)
+#define X86_DR7_G0 RT_BIT(1)
/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
-#define X86_DR7_L1 BIT(2)
+#define X86_DR7_L1 RT_BIT(2)
/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
-#define X86_DR7_G1 BIT(3)
+#define X86_DR7_G1 RT_BIT(3)
/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
-#define X86_DR7_L2 BIT(4)
+#define X86_DR7_L2 RT_BIT(4)
/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
-#define X86_DR7_G2 BIT(5)
+#define X86_DR7_G2 RT_BIT(5)
/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
-#define X86_DR7_L3 BIT(6)
+#define X86_DR7_L3 RT_BIT(6)
/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
-#define X86_DR7_G3 BIT(7)
+#define X86_DR7_G3 RT_BIT(7)
/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
-#define X86_DR7_LE BIT(8)
+#define X86_DR7_LE RT_BIT(8)
/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
-#define X86_DR7_GE BIT(9)
+#define X86_DR7_GE RT_BIT(9)
/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
* any DR register is accessed. */
-#define X86_DR7_GD BIT(13)
+#define X86_DR7_GD RT_BIT(13)
/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
#define X86_DR7_RW0_MASK (3 << 16)
/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
@@ -604,7 +604,7 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
#define X86_DR7_LEN3_MASK (3 << 30)
/** Bits which must be 1s. */
-#define X86_DR7_MB1_MASK (BIT(10))
+#define X86_DR7_MB1_MASK (RT_BIT(10))
/** Calcs the L bit of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
@@ -649,7 +649,7 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
/** Mask used to check if any breakpoints are enabled. */
-#define X86_DR7_ENABLED_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(7))
+#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
/** @} */
@@ -659,8 +659,8 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
*/
/** CPU Feature control. */
#define MSR_IA32_FEATURE_CONTROL 0x3A
-#define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
-#define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
+#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
+#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
@@ -704,19 +704,19 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
#define MSR_K6_EFER 0xc0000080
/** @todo document EFER */
/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
-#define MSR_K6_EFER_SCE BIT(0)
+#define MSR_K6_EFER_SCE RT_BIT(0)
/** Bit 8 - LME - Long mode enabled. (R/W) */
-#define MSR_K6_EFER_LME BIT(8)
+#define MSR_K6_EFER_LME RT_BIT(8)
/** Bit 10 - LMA - Long mode active. (R) */
-#define MSR_K6_EFER_LMA BIT(10)
+#define MSR_K6_EFER_LMA RT_BIT(10)
/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
-#define MSR_K6_EFER_NXE BIT(11)
+#define MSR_K6_EFER_NXE RT_BIT(11)
/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
-#define MSR_K6_EFER_SVME BIT(12)
+#define MSR_K6_EFER_SVME RT_BIT(12)
/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
-#define MSR_K6_EFER_LMSLE BIT(13)
+#define MSR_K6_EFER_LMSLE RT_BIT(13)
/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
-#define MSR_K6_EFER_FFXSR BIT(14)
+#define MSR_K6_EFER_FFXSR RT_BIT(14)
/** K6 STAR - SYSCALL/RET targets. */
#define MSR_K6_STAR 0xc0000081
/** Shift value for getting the SYSRET CS and SS value. */
@@ -767,7 +767,7 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
#define MSR_K8_TOP_MEM1 0xc001001a
#define MSR_K8_TOP_MEM2 0xc001001d
#define MSR_K8_VM_CR 0xc0010114
-#define MSR_K8_VM_CR_SVM_DISABLE BIT(4)
+#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
#define MSR_K8_IGNNE 0xc0010115
#define MSR_K8_SMM_CTL 0xc0010116
@@ -840,25 +840,25 @@ typedef X86PGPAEUINT *PX86PGPAEUINT;
* @{
*/
/** Bit 0 - P - Present bit. */
-#define X86_PTE_P BIT(0)
+#define X86_PTE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
-#define X86_PTE_RW BIT(1)
+#define X86_PTE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
-#define X86_PTE_US BIT(2)
+#define X86_PTE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
-#define X86_PTE_PWT BIT(3)
+#define X86_PTE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
-#define X86_PTE_PCD BIT(4)
+#define X86_PTE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
-#define X86_PTE_A BIT(5)
+#define X86_PTE_A RT_BIT(5)
/** Bit 6 - D - Dirty bit. */
-#define X86_PTE_D BIT(6)
+#define X86_PTE_D RT_BIT(6)
/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
-#define X86_PTE_PAT BIT(7)
+#define X86_PTE_PAT RT_BIT(7)
/** Bit 8 - G - Global flag. */
-#define X86_PTE_G BIT(8)
+#define X86_PTE_G RT_BIT(8)
/** Bits 9-11 - - Available for use to system software. */
-#define X86_PTE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
+#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PTE_PG_MASK ( 0xfffff000 )
@@ -1033,22 +1033,22 @@ typedef const X86PTPAE *PCX86PTPAE;
* @{
*/
/** Bit 0 - P - Present bit. */
-#define X86_PDE_P BIT(0)
+#define X86_PDE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
-#define X86_PDE_RW BIT(1)
+#define X86_PDE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
-#define X86_PDE_US BIT(2)
+#define X86_PDE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
-#define X86_PDE_PWT BIT(3)
+#define X86_PDE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
-#define X86_PDE_PCD BIT(4)
+#define X86_PDE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
-#define X86_PDE_A BIT(5)
+#define X86_PDE_A RT_BIT(5)
/** Bit 7 - PS - Page size attribute.
* Clear mean 4KB pages, set means large pages (2/4MB). */
-#define X86_PDE_PS BIT(7)
+#define X86_PDE_PS RT_BIT(7)
/** Bits 9-11 - - Available for use to system software. */
-#define X86_PDE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
+#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PDE_PG_MASK ( 0xfffff000 )
@@ -1143,27 +1143,27 @@ typedef const X86PDEPAEBITS *PCX86PDEPAE
* @{
*/
/** Bit 0 - P - Present bit. */
-#define X86_PDE4M_P BIT(0)
+#define X86_PDE4M_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
-#define X86_PDE4M_RW BIT(1)
+#define X86_PDE4M_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
-#define X86_PDE4M_US BIT(2)
+#define X86_PDE4M_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
-#define X86_PDE4M_PWT BIT(3)
+#define X86_PDE4M_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
-#define X86_PDE4M_PCD BIT(4)
+#define X86_PDE4M_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
-#define X86_PDE4M_A BIT(5)
+#define X86_PDE4M_A RT_BIT(5)
/** Bit 6 - D - Dirty bit. */
-#define X86_PDE4M_D BIT(6)
+#define X86_PDE4M_D RT_BIT(6)
/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
-#define X86_PDE4M_PS BIT(7)
+#define X86_PDE4M_PS RT_BIT(7)
/** Bit 8 - G - Global flag. */
-#define X86_PDE4M_G BIT(8)
+#define X86_PDE4M_G RT_BIT(8)
/** Bits 9-11 - AVL - Available for use to system software. */
-#define X86_PDE4M_AVL (BIT(9) | BIT(10) | BIT(11))
+#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
-#define X86_PDE4M_PAT BIT(12)
+#define X86_PDE4M_PAT RT_BIT(12)
/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
#define X86_PDE4M_PAT_SHIFT (12 - 7)
/** Bits 22-31 - - Physical Page number. */
@@ -1356,19 +1356,19 @@ typedef const X86PDPAE *PCX86PDPAE;
* @{
*/
/** Bit 0 - P - Present bit. */
-#define X86_PDPE_P BIT(0)
+#define X86_PDPE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
-#define X86_PDPE_RW BIT(1)
+#define X86_PDPE_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
-#define X86_PDPE_US BIT(2)
+#define X86_PDPE_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
-#define X86_PDPE_PWT BIT(3)
+#define X86_PDPE_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
-#define X86_PDPE_PCD BIT(4)
+#define X86_PDPE_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. Long Mode only. */
-#define X86_PDPE_A BIT(5)
+#define X86_PDPE_A RT_BIT(5)
/** Bits 9-11 - - Available for use to system software. */
-#define X86_PDPE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
+#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#if 1 /* we're using this internally and have to mask of the top 16-bit. */
#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
@@ -1463,19 +1463,19 @@ typedef const X86PDPTR *PCX86PDPTR;
* @{
*/
/** Bit 0 - P - Present bit. */
-#define X86_PML4E_P BIT(0)
+#define X86_PML4E_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
-#define X86_PML4E_RW BIT(1)
+#define X86_PML4E_RW RT_BIT(1)
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
-#define X86_PML4E_US BIT(2)
+#define X86_PML4E_US RT_BIT(2)
/** Bit 3 - PWT - Page level write thru bit. */
-#define X86_PML4E_PWT BIT(3)
+#define X86_PML4E_PWT RT_BIT(3)
/** Bit 4 - PCD - Page level cache disable bit. */
-#define X86_PML4E_PCD BIT(4)
+#define X86_PML4E_PCD RT_BIT(4)
/** Bit 5 - A - Access bit. */
-#define X86_PML4E_A BIT(5)
+#define X86_PML4E_A RT_BIT(5)
/** Bits 9-11 - - Available for use to system software. */
-#define X86_PML4E_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
+#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
#if 1 /* we're using this internally and have to mask of the top 16-bit. */
#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
@@ -1948,7 +1948,7 @@ typedef X86DESC *PX86DESCHC;
/** Code(=set)/Data(=clear) bit. */
#define X86_SEL_TYPE_CODE 8
/** Memory(=set)/System(=clear) bit. */
-#define X86_SEL_TYPE_MEMORY BIT(4)
+#define X86_SEL_TYPE_MEMORY RT_BIT(4)
/** Accessed bit. */
#define X86_SEL_TYPE_ACCESSED 1
/** Expand down bit (for data selectors only). */
@@ -2053,20 +2053,20 @@ typedef X86DESC *PX86DESCHC;
* These are for the 2nd 32-bit word of a descriptor.
* @{ */
/** Bits 8-11 - TYPE - Descriptor type mask. */
-#define X86_DESC_TYPE_MASK (BIT(8) | BIT(9) | BIT(10) | BIT(11))
+#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
/** Bit 12 - S - System (=0) or Code/Data (=1). */
-#define X86_DESC_S BIT(12)
+#define X86_DESC_S RT_BIT(12)
/** Bits 13-14 - DPL - Descriptor Privilege Level. */
-#define X86_DESC_DPL (BIT(13) | BIT(14))
+#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
/** Bit 15 - P - Present. */
-#define X86_DESC_P BIT(15)
+#define X86_DESC_P RT_BIT(15)
/** Bit 20 - AVL - Available for system software. */
-#define X86_DESC_AVL BIT(20)
+#define X86_DESC_AVL RT_BIT(20)
/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
-#define X86_DESC_DB BIT(22)
+#define X86_DESC_DB RT_BIT(22)
/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
* used, if clear byte. */
-#define X86_DESC_G BIT(23)
+#define X86_DESC_G RT_BIT(23)
/** @} */
/** @} */
@@ -2180,15 +2180,15 @@ typedef const X86XCPT *PCX86XCPT;
* @{
*/
/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
-#define X86_TRAP_PF_P BIT(0)
+#define X86_TRAP_PF_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) or write (set) access. */
-#define X86_TRAP_PF_RW BIT(1)
+#define X86_TRAP_PF_RW RT_BIT(1)
/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
-#define X86_TRAP_PF_US BIT(2)
+#define X86_TRAP_PF_US RT_BIT(2)
/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
-#define X86_TRAP_PF_RSVD BIT(3)
+#define X86_TRAP_PF_RSVD RT_BIT(3)
/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
-#define X86_TRAP_PF_ID BIT(4)
+#define X86_TRAP_PF_ID RT_BIT(4)
/** @} */
#pragma pack(1)
--- VirtualBox-1.5.2_OSE/include/VBox/VBoxDev.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/VBoxDev.h 2007-12-03 12:07:19.000000000 +0100
@@ -24,33 +24,33 @@ __BEGIN_DECLS
/** Mouse capability bits
* @{ */
/** the guest requests absolute mouse coordinates (guest additions installed) */
-#define VMMDEV_MOUSEGUESTWANTSABS BIT(0)
+#define VMMDEV_MOUSEGUESTWANTSABS RT_BIT(0)
/** the host wants to send absolute mouse coordinates (input not captured) */
-#define VMMDEV_MOUSEHOSTWANTSABS BIT(1)
+#define VMMDEV_MOUSEHOSTWANTSABS RT_BIT(1)
/** the guest needs a hardware cursor on host. When guest additions are installed
* and the host has promised to display the cursor itself, the guest installs a
* hardware mouse driver. Don't ask the guest to switch to a software cursor then. */
-#define VMMDEV_MOUSEGUESTNEEDSHOSTCUR BIT(2)
+#define VMMDEV_MOUSEGUESTNEEDSHOSTCUR RT_BIT(2)
/** the host is NOT able to draw the cursor itself (e.g. L4 console) */
-#define VMMDEV_MOUSEHOSTCANNOTHWPOINTER BIT(3)
+#define VMMDEV_MOUSEHOSTCANNOTHWPOINTER RT_BIT(3)
/** @} */
/** Flags for pfnSetCredentials
* @{ */
/** the guest should perform a logon with the credentials */
-#define VMMDEV_SETCREDENTIALS_GUESTLOGON BIT(0)
+#define VMMDEV_SETCREDENTIALS_GUESTLOGON RT_BIT(0)
/** the guest should prevent local logons */
-#define VMMDEV_SETCREDENTIALS_NOLOCALLOGON BIT(1)
+#define VMMDEV_SETCREDENTIALS_NOLOCALLOGON RT_BIT(1)
/** the guest should verify the credentials */
-#define VMMDEV_SETCREDENTIALS_JUDGE BIT(15)
+#define VMMDEV_SETCREDENTIALS_JUDGE RT_BIT(15)
/** @} */
/** Guest capability bits
* @{ */
/** the guest supports seamless display rendering */
-#define VMMDEV_GUEST_SUPPORTS_SEAMLESS BIT(0)
+#define VMMDEV_GUEST_SUPPORTS_SEAMLESS RT_BIT(0)
/** the guest supports mapping guest to host windows */
-#define VMMDEV_GUEST_SUPPORTS_GUEST_HOST_WINDOW_MAPPING BIT(1)
+#define VMMDEV_GUEST_SUPPORTS_GUEST_HOST_WINDOW_MAPPING RT_BIT(1)
/** @} */
/** Size of VMMDev RAM region accessible by guest.
--- VirtualBox-1.5.2_OSE/include/VBox/dis.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/dis.h 2007-12-03 12:07:19.000000000 +0100
@@ -57,63 +57,63 @@ __BEGIN_DECLS
/**
* Operand type.
*/
-#define OPTYPE_INVALID BIT(0)
-#define OPTYPE_HARMLESS BIT(1)
-#define OPTYPE_CONTROLFLOW BIT(2)
-#define OPTYPE_POTENTIALLY_DANGEROUS BIT(3)
-#define OPTYPE_DANGEROUS BIT(4)
-#define OPTYPE_PORTIO BIT(5)
-#define OPTYPE_PRIVILEGED BIT(6)
-#define OPTYPE_PRIVILEGED_NOTRAP BIT(7)
-#define OPTYPE_UNCOND_CONTROLFLOW BIT(8)
-#define OPTYPE_RELATIVE_CONTROLFLOW BIT(9)
-#define OPTYPE_COND_CONTROLFLOW BIT(10)
-#define OPTYPE_INTERRUPT BIT(11)
-#define OPTYPE_ILLEGAL BIT(12)
-#define OPTYPE_RRM_DANGEROUS BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
-#define OPTYPE_RRM_DANGEROUS_16 BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
+#define OPTYPE_INVALID RT_BIT(0)
+#define OPTYPE_HARMLESS RT_BIT(1)
+#define OPTYPE_CONTROLFLOW RT_BIT(2)
+#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
+#define OPTYPE_DANGEROUS RT_BIT(4)
+#define OPTYPE_PORTIO RT_BIT(5)
+#define OPTYPE_PRIVILEGED RT_BIT(6)
+#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
+#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
+#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
+#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
+#define OPTYPE_INTERRUPT RT_BIT(11)
+#define OPTYPE_ILLEGAL RT_BIT(12)
+#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
+#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
-#define OPTYPE_INHIBIT_IRQS BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
-#define OPTYPE_PORTIO_READ BIT(17)
-#define OPTYPE_PORTIO_WRITE BIT(18)
+#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
+#define OPTYPE_PORTIO_READ RT_BIT(17)
+#define OPTYPE_PORTIO_WRITE RT_BIT(18)
#define OPTYPE_ALL (0xffffffff)
/** Parameter usage flags.
* @{
*/
-#define USE_BASE BIT(0)
-#define USE_INDEX BIT(1)
-#define USE_SCALE BIT(2)
-#define USE_REG_GEN8 BIT(3)
-#define USE_REG_GEN16 BIT(4)
-#define USE_REG_GEN32 BIT(5)
-#define USE_REG_FP BIT(6)
-#define USE_REG_MMX BIT(7)
-#define USE_REG_XMM BIT(8)
-#define USE_REG_CR BIT(9)
-#define USE_REG_DBG BIT(10)
-#define USE_REG_SEG BIT(11)
-#define USE_REG_TEST BIT(12)
-#define USE_DISPLACEMENT8 BIT(13)
-#define USE_DISPLACEMENT16 BIT(14)
-#define USE_DISPLACEMENT32 BIT(15)
-#define USE_IMMEDIATE8 BIT(16)
-#define USE_IMMEDIATE8_REL BIT(17)
-#define USE_IMMEDIATE16 BIT(18)
-#define USE_IMMEDIATE16_REL BIT(19)
-#define USE_IMMEDIATE32 BIT(20)
-#define USE_IMMEDIATE32_REL BIT(21)
-#define USE_IMMEDIATE64 BIT(22)
-#define USE_IMMEDIATE_ADDR_0_32 BIT(23)
-#define USE_IMMEDIATE_ADDR_16_32 BIT(24)
-#define USE_IMMEDIATE_ADDR_0_16 BIT(25)
-#define USE_IMMEDIATE_ADDR_16_16 BIT(26)
+#define USE_BASE RT_BIT(0)
+#define USE_INDEX RT_BIT(1)
+#define USE_SCALE RT_BIT(2)
+#define USE_REG_GEN8 RT_BIT(3)
+#define USE_REG_GEN16 RT_BIT(4)
+#define USE_REG_GEN32 RT_BIT(5)
+#define USE_REG_FP RT_BIT(6)
+#define USE_REG_MMX RT_BIT(7)
+#define USE_REG_XMM RT_BIT(8)
+#define USE_REG_CR RT_BIT(9)
+#define USE_REG_DBG RT_BIT(10)
+#define USE_REG_SEG RT_BIT(11)
+#define USE_REG_TEST RT_BIT(12)
+#define USE_DISPLACEMENT8 RT_BIT(13)
+#define USE_DISPLACEMENT16 RT_BIT(14)
+#define USE_DISPLACEMENT32 RT_BIT(15)
+#define USE_IMMEDIATE8 RT_BIT(16)
+#define USE_IMMEDIATE8_REL RT_BIT(17)
+#define USE_IMMEDIATE16 RT_BIT(18)
+#define USE_IMMEDIATE16_REL RT_BIT(19)
+#define USE_IMMEDIATE32 RT_BIT(20)
+#define USE_IMMEDIATE32_REL RT_BIT(21)
+#define USE_IMMEDIATE64 RT_BIT(22)
+#define USE_IMMEDIATE_ADDR_0_32 RT_BIT(23)
+#define USE_IMMEDIATE_ADDR_16_32 RT_BIT(24)
+#define USE_IMMEDIATE_ADDR_0_16 RT_BIT(25)
+#define USE_IMMEDIATE_ADDR_16_16 RT_BIT(26)
/** DS:ESI */
-#define USE_POINTER_DS_BASED BIT(27)
+#define USE_POINTER_DS_BASED RT_BIT(27)
/** ES:EDI */
-#define USE_POINTER_ES_BASED BIT(28)
-#define USE_IMMEDIATE16_SX8 BIT(29)
-#define USE_IMMEDIATE32_SX8 BIT(30)
+#define USE_POINTER_ES_BASED RT_BIT(28)
+#define USE_IMMEDIATE16_SX8 RT_BIT(29)
+#define USE_IMMEDIATE32_SX8 RT_BIT(30)
#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
@@ -213,12 +213,12 @@ __BEGIN_DECLS
/** Used by DISQueryParamVal & EMIQueryParamVal
* @{
*/
-#define PARAM_VAL8 BIT(0)
-#define PARAM_VAL16 BIT(1)
-#define PARAM_VAL32 BIT(2)
-#define PARAM_VAL64 BIT(3)
-#define PARAM_VALFARPTR16 BIT(4)
-#define PARAM_VALFARPTR32 BIT(5)
+#define PARAM_VAL8 RT_BIT(0)
+#define PARAM_VAL16 RT_BIT(1)
+#define PARAM_VAL32 RT_BIT(2)
+#define PARAM_VAL64 RT_BIT(3)
+#define PARAM_VALFARPTR16 RT_BIT(4)
+#define PARAM_VALFARPTR32 RT_BIT(5)
#define PARMTYPE_REGISTER 1
#define PARMTYPE_ADDRESS 2
--- VirtualBox-1.5.2_OSE/include/VBox/vm.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/VBox/vm.h 2007-12-03 12:07:19.000000000 +0100
@@ -42,57 +42,57 @@
* @{
*/
/** This action forces the VM to service check and pending interrups on the APIC. */
-#define VM_FF_INTERRUPT_APIC BIT(0)
+#define VM_FF_INTERRUPT_APIC RT_BIT(0)
/** This action forces the VM to service check and pending interrups on the PIC. */
-#define VM_FF_INTERRUPT_PIC BIT(1)
+#define VM_FF_INTERRUPT_PIC RT_BIT(1)
/** This action forces the VM to schedule and run pending timer (TM). */
-#define VM_FF_TIMER BIT(2)
+#define VM_FF_TIMER RT_BIT(2)
/** PDM Queues are pending. */
-#define VM_FF_PDM_QUEUES BIT(3)
+#define VM_FF_PDM_QUEUES RT_BIT(3)
/** PDM DMA transfers are pending. */
-#define VM_FF_PDM_DMA BIT(4)
+#define VM_FF_PDM_DMA RT_BIT(4)
/** PDM critical section unlocking is pending, process promptly upon return to R3. */
-#define VM_FF_PDM_CRITSECT BIT(5)
+#define VM_FF_PDM_CRITSECT RT_BIT(5)
/** This action forces the VM to call DBGF so DBGF can service debugger
* requests in the emulation thread.
* This action flag stays asserted till DBGF clears it.*/
-#define VM_FF_DBGF BIT(8)
+#define VM_FF_DBGF RT_BIT(8)
/** This action forces the VM to service pending requests from other
* thread or requests which must be executed in another context. */
-#define VM_FF_REQUEST BIT(9)
+#define VM_FF_REQUEST RT_BIT(9)
/** Terminate the VM immediately. */
-#define VM_FF_TERMINATE BIT(10)
+#define VM_FF_TERMINATE RT_BIT(10)
/** Reset the VM. (postponed) */
-#define VM_FF_RESET BIT(11)
+#define VM_FF_RESET RT_BIT(11)
/** This action forces the VM to resync the page tables before going
* back to execute guest code. (GLOBAL FLUSH) */
-#define VM_FF_PGM_SYNC_CR3 BIT(16)
+#define VM_FF_PGM_SYNC_CR3 RT_BIT(16)
/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
* (NON-GLOBAL FLUSH) */
-#define VM_FF_PGM_SYNC_CR3_NON_GLOBAL BIT(17)
+#define VM_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT(17)
/** Check the interupt and trap gates */
-#define VM_FF_TRPM_SYNC_IDT BIT(18)
+#define VM_FF_TRPM_SYNC_IDT RT_BIT(18)
/** Check Guest's TSS ring 0 stack */
-#define VM_FF_SELM_SYNC_TSS BIT(19)
+#define VM_FF_SELM_SYNC_TSS RT_BIT(19)
/** Check Guest's GDT table */
-#define VM_FF_SELM_SYNC_GDT BIT(20)
+#define VM_FF_SELM_SYNC_GDT RT_BIT(20)
/** Check Guest's LDT table */
-#define VM_FF_SELM_SYNC_LDT BIT(21)
+#define VM_FF_SELM_SYNC_LDT RT_BIT(21)
/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
-#define VM_FF_INHIBIT_INTERRUPTS BIT(22)
+#define VM_FF_INHIBIT_INTERRUPTS RT_BIT(22)
/** CSAM needs to scan the page that's being executed */
-#define VM_FF_CSAM_SCAN_PAGE BIT(24)
+#define VM_FF_CSAM_SCAN_PAGE RT_BIT(24)
/** CSAM needs to do some homework. */
-#define VM_FF_CSAM_PENDING_ACTION BIT(25)
+#define VM_FF_CSAM_PENDING_ACTION RT_BIT(25)
/** Force return to Ring-3. */
-#define VM_FF_TO_R3 BIT(28)
+#define VM_FF_TO_R3 RT_BIT(28)
/** Suspend the VM - debug only. */
-#define VM_FF_DEBUG_SUSPEND BIT(31)
+#define VM_FF_DEBUG_SUSPEND RT_BIT(31)
/** Externally forced actions. Used to quit the idle/wait loop. */
#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_REQUEST)
--- VirtualBox-1.5.2_OSE/include/iprt/path.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/path.h 2007-12-03 12:07:19.000000000 +0100
@@ -482,7 +482,7 @@ RTR3DECL(int) RTPathGetOwner(const char
/** @name RTPathRename, RTDirRename & RTFileRename flags.
* @{ */
/** This will replace attempt any target which isn't a directory. */
-#define RTPATHRENAME_FLAGS_REPLACE BIT(0)
+#define RTPATHRENAME_FLAGS_REPLACE RT_BIT(0)
/** @} */
/**
--- VirtualBox-1.5.2_OSE/include/iprt/uni.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/uni.h 2007-12-03 12:07:19.000000000 +0100
@@ -91,13 +91,13 @@ typedef const RTUNICASERANGE *PCRTUNICAS
/** @name Unicode Code Point Flags.
* @internal
* @{ */
-#define RTUNI_UPPER BIT(0)
-#define RTUNI_LOWER BIT(1)
-#define RTUNI_ALPHA BIT(2)
-#define RTUNI_XDIGIT BIT(3)
-#define RTUNI_DDIGIT BIT(4)
-#define RTUNI_WSPACE BIT(5)
-/*#define RTUNI_BSPACE BIT(6) - later */
+#define RTUNI_UPPER RT_BIT(0)
+#define RTUNI_LOWER RT_BIT(1)
+#define RTUNI_ALPHA RT_BIT(2)
+#define RTUNI_XDIGIT RT_BIT(3)
+#define RTUNI_DDIGIT RT_BIT(4)
+#define RTUNI_WSPACE RT_BIT(5)
+/*#define RTUNI_BSPACE RT_BIT(6) - later */
/** @} */
--- VirtualBox-1.5.2_OSE/include/iprt/ldr.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/ldr.h 2007-12-03 12:07:19.000000000 +0100
@@ -231,7 +231,7 @@ RTDECL(int) RTLdrEnumSymbols(RTLDRMOD hL
/** @name RTLdrEnumSymbols flags.
* @{ */
/** Returns ALL kinds of symbols. The default is to only return public/exported symbols. */
-#define RTLDR_ENUM_SYMBOL_FLAGS_ALL BIT(1)
+#define RTLDR_ENUM_SYMBOL_FLAGS_ALL RT_BIT(1)
/** @} */
__END_DECLS
--- VirtualBox-1.5.2_OSE/include/iprt/time.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/time.h 2007-12-03 12:07:19.000000000 +0100
@@ -568,15 +568,15 @@ typedef const RTTIME *PCRTTIME;
/** Set if the time is local and daylight saving time is in effect.
* Not bit is not valid if RTTIME_FLAGS_NO_DST_DATA is set. */
-#define RTTIME_FLAGS_DST BIT(4)
+#define RTTIME_FLAGS_DST RT_BIT(4)
/** Set if the time is local and there is no data available on daylight saving time. */
-#define RTTIME_FLAGS_NO_DST_DATA BIT(5)
+#define RTTIME_FLAGS_NO_DST_DATA RT_BIT(5)
/** Set if the year is a leap year.
* This is mutual exclusiv with RTTIME_FLAGS_COMMON_YEAR. */
-#define RTTIME_FLAGS_LEAP_YEAR BIT(6)
+#define RTTIME_FLAGS_LEAP_YEAR RT_BIT(6)
/** Set if the year is a common year.
* This is mutual exclusiv with RTTIME_FLAGS_LEAP_YEAR. */
-#define RTTIME_FLAGS_COMMON_YEAR BIT(7)
+#define RTTIME_FLAGS_COMMON_YEAR RT_BIT(7)
/** @} */
--- VirtualBox-1.5.2_OSE/include/iprt/asm.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/asm.h 2007-12-03 12:07:19.000000000 +0100
@@ -1999,7 +1999,7 @@ DECLASM(uint128_t) ASMAtomicXchgU128(vol
# else
DECLINLINE(uint128_t) ASMAtomicXchgU128(volatile uint128_t *pu128, uint128_t u128)
{
- if (true)/*ASMCpuId_ECX(1) & BIT(13))*/
+ if (true)/*ASMCpuId_ECX(1) & RT_BIT(13))*/
{
/** @todo this is clumsy code */
RTUINT128U u128Ret;
--- VirtualBox-1.5.2_OSE/include/iprt/timer.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/timer.h 2007-12-03 12:07:19.000000000 +0100
@@ -105,7 +105,7 @@ RTDECL(int) RTTimerCreateEx(PRTTIMER *pp
/** Any CPU is fine. (Must be 0.) */
#define RTTIMER_FLAGS_CPU_ANY 0
/** One specific CPU */
-#define RTTIMER_FLAGS_CPU_SPECIFIC BIT(8)
+#define RTTIMER_FLAGS_CPU_SPECIFIC RT_BIT(8)
/** All online CPUs. */
#define RTTIMER_FLAGS_CPU_ALL ( RTTIMER_FLAGS_CPU_MASK | RTTIMER_FLAGS_CPU_SPECIFIC )
/** CPU mask. */
--- VirtualBox-1.5.2_OSE/include/iprt/string.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/string.h 2007-12-03 12:07:19.000000000 +0100
@@ -325,7 +325,7 @@ RTDECL(char *) RTStrPutCpInternal(char *
DECLINLINE(RTUNICP) RTStrGetCp(const char *psz)
{
const unsigned char uch = *(const unsigned char *)psz;
- if (!(uch & BIT(7)))
+ if (!(uch & RT_BIT(7)))
return uch;
return RTStrGetCpInternal(psz);
}
@@ -346,7 +346,7 @@ DECLINLINE(RTUNICP) RTStrGetCp(const cha
DECLINLINE(int) RTStrGetCpEx(const char **ppsz, PRTUNICP pCp)
{
const unsigned char uch = **(const unsigned char **)ppsz;
- if (!(uch & BIT(7)))
+ if (!(uch & RT_BIT(7)))
{
(*ppsz)++;
*pCp = uch;
--- VirtualBox-1.5.2_OSE/include/iprt/thread.h.2.6.24 2007-08-30 17:16:21.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/thread.h 2007-12-03 12:07:19.000000000 +0100
@@ -172,12 +172,12 @@ typedef enum RTTHREADFLAGS
* This flag is used to keep the thread structure around so it can
* be waited on after termination.
*/
- RTTHREADFLAGS_WAITABLE = BIT(0),
+ RTTHREADFLAGS_WAITABLE = RT_BIT(0),
/** The bit number corresponding to the RTTHREADFLAGS_WAITABLE mask. */
RTTHREADFLAGS_WAITABLE_BIT = 0,
/** Mask of valid flags, use for validation. */
- RTTHREADFLAGS_MASK = BIT(0)
+ RTTHREADFLAGS_MASK = RT_BIT(0)
} RTTHREADFLAGS;
--- VirtualBox-1.5.2_OSE/include/iprt/types.h.2.6.24 2007-10-18 13:07:28.000000000 +0200
+++ VirtualBox-1.5.2_OSE/include/iprt/types.h 2007-12-03 12:07:19.000000000 +0100
@@ -69,6 +69,7 @@
# define bool linux_bool
# define true linux_true
# define false linux_false
+# include <linux/autoconf.h>
# include <linux/types.h>
# include <linux/stddef.h>
# undef false
--- VirtualBox-1.5.2_OSE/src/VBox/HostDrivers/Support/linux/Makefile.2.6.24 2007-12-03 12:07:19.000000000 +0100
+++ VirtualBox-1.5.2_OSE/src/VBox/HostDrivers/Support/linux/Makefile 2007-12-03 12:09:01.000000000 +0100
@@ -148,6 +148,8 @@ endif
#
KFLAGS += -DVBOX_WITHOUT_IDT_PATCHING
+KFLAGS += -D_INTPTR_T_DECLARED
+
#
# Use the RTR0MemObj API - testing.
# If this makes testboxes crash/burn/leak disable it and add a comment to defect #2116.
--- VirtualBox-1.5.2_OSE/src/VBox/HostDrivers/Support/SUPDRVShared.c.2.6.24 2007-10-18 13:07:28.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/HostDrivers/Support/SUPDRVShared.c 2007-12-03 12:07:19.000000000 +0100
@@ -65,23 +65,23 @@ typedef enum VMMR0OPERATION
*******************************************************************************/
/* from x86.h - clashes with linux thus this duplication */
#undef X86_CR0_PG
-#define X86_CR0_PG BIT(31)
+#define X86_CR0_PG RT_BIT(31)
#undef X86_CR0_PE
-#define X86_CR0_PE BIT(0)
+#define X86_CR0_PE RT_BIT(0)
#undef X86_CPUID_AMD_FEATURE_EDX_NX
-#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
+#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
#undef MSR_K6_EFER
#define MSR_K6_EFER 0xc0000080
#undef MSR_K6_EFER_NXE
-#define MSR_K6_EFER_NXE BIT(11)
+#define MSR_K6_EFER_NXE RT_BIT(11)
#undef MSR_K6_EFER_LMA
-#define MSR_K6_EFER_LMA BIT(10)
+#define MSR_K6_EFER_LMA RT_BIT(10)
#undef X86_CR4_PGE
-#define X86_CR4_PGE BIT(7)
+#define X86_CR4_PGE RT_BIT(7)
#undef X86_CR4_PAE
-#define X86_CR4_PAE BIT(5)
+#define X86_CR4_PAE RT_BIT(5)
#undef X86_CPUID_AMD_FEATURE_EDX_LONG_MODE
-#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
+#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
/** The frequency by which we recalculate the u32UpdateHz and
@@ -4127,9 +4127,9 @@ static int supdrvIOCtl_GetPagingMode(PSU
{
uint64_t efer = ASMRdMsr(MSR_K6_EFER);
if ((fAmdFeatures & X86_CPUID_AMD_FEATURE_EDX_NX) && (efer & MSR_K6_EFER_NXE))
- fNXEPlusLMA |= BIT(0);
+ fNXEPlusLMA |= RT_BIT(0);
if ((fAmdFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE) && (efer & MSR_K6_EFER_LMA))
- fNXEPlusLMA |= BIT(1);
+ fNXEPlusLMA |= RT_BIT(1);
}
}
@@ -4147,7 +4147,7 @@ static int supdrvIOCtl_GetPagingMode(PSU
pOut->enmMode = SUPPAGINGMODE_PAE;
break;
- case X86_CR4_PAE | BIT(0):
+ case X86_CR4_PAE | RT_BIT(0):
pOut->enmMode = SUPPAGINGMODE_PAE_NX;
break;
@@ -4155,23 +4155,23 @@ static int supdrvIOCtl_GetPagingMode(PSU
pOut->enmMode = SUPPAGINGMODE_PAE_GLOBAL;
break;
- case X86_CR4_PAE | X86_CR4_PGE | BIT(0):
+ case X86_CR4_PAE | X86_CR4_PGE | RT_BIT(0):
pOut->enmMode = SUPPAGINGMODE_PAE_GLOBAL;
break;
- case BIT(1) | X86_CR4_PAE:
+ case RT_BIT(1) | X86_CR4_PAE:
pOut->enmMode = SUPPAGINGMODE_AMD64;
break;
- case BIT(1) | X86_CR4_PAE | BIT(0):
+ case RT_BIT(1) | X86_CR4_PAE | RT_BIT(0):
pOut->enmMode = SUPPAGINGMODE_AMD64_NX;
break;
- case BIT(1) | X86_CR4_PAE | X86_CR4_PGE:
+ case RT_BIT(1) | X86_CR4_PAE | X86_CR4_PGE:
pOut->enmMode = SUPPAGINGMODE_AMD64_GLOBAL;
break;
- case BIT(1) | X86_CR4_PAE | X86_CR4_PGE | BIT(0):
+ case RT_BIT(1) | X86_CR4_PAE | X86_CR4_PGE | RT_BIT(0):
pOut->enmMode = SUPPAGINGMODE_AMD64_GLOBAL_NX;
break;
@@ -4518,7 +4518,7 @@ static SUPGIPMODE supdrvGipDeterminTscMo
if (uEAX >= 0x80000007)
{
ASMCpuId(0x80000007, &uEAX, &uEBX, &uECX, &uEDX);
- if ( !(uEDX & BIT(8))/* TscInvariant */
+ if ( !(uEDX & RT_BIT(8))/* TscInvariant */
&& (uEDX & 0x3e)) /* STC|TM|THERMTRIP|VID|FID. Ignore TS. */
return SUPGIPMODE_ASYNC_TSC;
}
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/VMMAll/PGMAllBth.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/VMMAll/PGMAllBth.h 2007-12-03 12:07:19.000000000 +0100
@@ -1955,7 +1955,7 @@ PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsig
{
GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
- GCPhys |= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
+ GCPhys |= GCPtrPage & RT_BIT(X86_PAGE_2M_SHIFT);
# endif
rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
}
@@ -3012,7 +3012,7 @@ PGM_BTH_DECL(unsigned, AssertCR3)(PVM pV
}
GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
- GCPhysGst |= GCPtr & BIT(X86_PAGE_2M_SHIFT);
+ GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
# endif
}
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/VMMR0/HWVMXR0.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/VMMR0/HWVMXR0.h 2007-12-03 12:07:19.000000000 +0100
@@ -102,7 +102,7 @@ HWACCMR0DECL(int) VMXR0RunGuestCode(PVM
if (pCtx->reg && pCtx->reg##Hid.Attr.n.u1Present == 1) \
val = pCtx->reg##Hid.Attr.u | X86_SEL_TYPE_ACCESSED; \
else \
- val = 0x10000; /* Invalid guest state error otherwise. (BIT(16) = Unusable) */ \
+ val = 0x10000; /* Invalid guest state error otherwise. (RT_BIT(16) = Unusable) */ \
\
rc |= VMXWriteVMCS(VMX_VMCS_GUEST_##REG##_ACCESS_RIGHTS, val);
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/PATM/PATMA.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/PATM/PATMA.h 2007-12-03 12:07:19.000000000 +0100
@@ -95,9 +95,9 @@
#define PATM_ACTION_MAGIC 0xABCD4321
/** PATM_TEMP_RESTORE_FLAGS */
-#define PATM_RESTORE_EAX BIT(0)
-#define PATM_RESTORE_ECX BIT(1)
-#define PATM_RESTORE_EDI BIT(2)
+#define PATM_RESTORE_EAX RT_BIT(0)
+#define PATM_RESTORE_ECX RT_BIT(1)
+#define PATM_RESTORE_EDI RT_BIT(2)
typedef struct
{
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/PATM/PATMInternal.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/PATM/PATMInternal.h 2007-12-03 12:07:19.000000000 +0100
@@ -40,7 +40,7 @@
#define MAX_PATCH_SIZE (1024*4)
/*
- * Internal patch type flags (starts at BIT(11))
+ * Internal patch type flags (starts at RT_BIT(11))
*/
#define PATMFL_CHECK_SIZE BIT64(11)
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/CPUMInternal.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/CPUMInternal.h 2007-12-03 12:07:19.000000000 +0100
@@ -49,7 +49,7 @@
/** Type mask. */
#define CPUM_HANDLER_TYPEMASK 0xff
/** If set EBP points to the CPUMCTXCORE that's being used. */
-#define CPUM_HANDLER_CTXCORE_IN_EBP BIT(31)
+#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
/** @} */
@@ -57,18 +57,18 @@
* (Don't forget to sync this with CPUMInternal.mac!)
* @{ */
/** Used the FPU, SSE or such stuff. */
-#define CPUM_USED_FPU BIT(0)
+#define CPUM_USED_FPU RT_BIT(0)
/** Used the FPU, SSE or such stuff since last we were in REM.
* REM syncing is clearing this, lazy FPU is setting it. */
-#define CPUM_USED_FPU_SINCE_REM BIT(1)
+#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
/** Host OS is using SYSENTER and we must NULL the CS. */
-#define CPUM_USE_SYSENTER BIT(2)
+#define CPUM_USE_SYSENTER RT_BIT(2)
/** Host OS is using SYSENTER and we must NULL the CS. */
-#define CPUM_USE_SYSCALL BIT(3)
+#define CPUM_USE_SYSCALL RT_BIT(3)
/** Debug registers are used by host and must be disabled. */
-#define CPUM_USE_DEBUG_REGS_HOST BIT(4)
+#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
/** Enabled use of debug registers in guest context. */
-#define CPUM_USE_DEBUG_REGS BIT(5)
+#define CPUM_USE_DEBUG_REGS RT_BIT(5)
/** @} */
/* Sanity check. */
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/HWACCMInternal.h.2.6.24 2007-10-18 13:07:28.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/HWACCMInternal.h 2007-12-03 12:07:19.000000000 +0100
@@ -52,18 +52,18 @@ __BEGIN_DECLS
* have been changed since last they were reset.
* @{
*/
-#define HWACCM_CHANGED_GUEST_FPU BIT(0)
-#define HWACCM_CHANGED_GUEST_CR0 BIT(1)
-#define HWACCM_CHANGED_GUEST_CR3 BIT(2)
-#define HWACCM_CHANGED_GUEST_CR4 BIT(3)
-#define HWACCM_CHANGED_GUEST_GDTR BIT(4)
-#define HWACCM_CHANGED_GUEST_IDTR BIT(5)
-#define HWACCM_CHANGED_GUEST_LDTR BIT(6)
-#define HWACCM_CHANGED_GUEST_TR BIT(7)
-#define HWACCM_CHANGED_GUEST_SYSENTER_MSR BIT(8)
-#define HWACCM_CHANGED_GUEST_SEGMENT_REGS BIT(9)
-#define HWACCM_CHANGED_GUEST_DEBUG BIT(10)
-#define HWACCM_CHANGED_HOST_CONTEXT BIT(11)
+#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
+#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
+#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
+#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
+#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
+#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
+#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
+#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
+#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
+#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
+#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
+#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
| HWACCM_CHANGED_GUEST_CR0 \
@@ -97,10 +97,10 @@ __BEGIN_DECLS
* Currently #NM and #PF only
*/
#ifdef VBOX_STRICT
-#define HWACCM_VMX_TRAP_MASK BIT(0) | BIT(7) | BIT(14) | BIT(6) | BIT(11) | BIT(12) | BIT(13) | BIT(16)
+#define HWACCM_VMX_TRAP_MASK RT_BIT(0) | RT_BIT(7) | RT_BIT(14) | RT_BIT(6) | RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(16)
#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
#else
-#define HWACCM_VMX_TRAP_MASK BIT(7) | BIT(14)
+#define HWACCM_VMX_TRAP_MASK RT_BIT(7) | RT_BIT(14)
#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
#endif
/** @} */
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/PGMInternal.h.2.6.24 2007-08-31 14:42:12.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/PGMInternal.h 2007-12-03 12:07:19.000000000 +0100
@@ -415,11 +415,11 @@ typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VI
/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
* node is in the tree. */
-#define PGMPHYS2VIRTHANDLER_IN_TREE BIT(0)
+#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
* node is in the head of an alias chain.
* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
-#define PGMPHYS2VIRTHANDLER_IS_HEAD BIT(1)
+#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
@@ -1734,13 +1734,13 @@ typedef struct PGM
* @{
*/
/** Updates the MM_RAM_FLAGS_VIRTUAL_HANDLER page bit. */
-#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL BIT(0)
+#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
/** Always sync CR3. */
-#define PGM_SYNC_ALWAYS BIT(1)
+#define PGM_SYNC_ALWAYS RT_BIT(1)
/** Check monitoring on next CR3 (re)load and invalidate page. */
-#define PGM_SYNC_MONITOR_CR3 BIT(2)
+#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
/** Clear the page pool (a light weight flush). */
-#define PGM_SYNC_CLEAR_PGM_POOL BIT(8)
+#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
/** @} */
--- VirtualBox-1.5.2_OSE/src/VBox/VMM/TRPMInternal.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/VMM/TRPMInternal.h 2007-12-03 12:07:19.000000000 +0100
@@ -59,9 +59,9 @@ __BEGIN_DECLS
/** Traps on IRET. */
#define TRPM_TRAP_IN_IRET 5
/** Set if this is a V86 resume. */
-#define TRPM_TRAP_IN_V86 BIT(30)
+#define TRPM_TRAP_IN_V86 RT_BIT(30)
/** If set this is a hypervisor register set. If cleared it's a guest set. */
-#define TRPM_TRAP_IN_HYPER BIT(31)
+#define TRPM_TRAP_IN_HYPER RT_BIT(31)
/** @} */
--- VirtualBox-1.5.2_OSE/src/VBox/Devices/Storage/fdc.c.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/Devices/Storage/fdc.c 2007-12-03 12:07:19.000000000 +0100
@@ -788,10 +788,10 @@ static uint32_t fdctrl_read_dor (fdctrl_
#else
/* bit4: 0 = drive 0 motor off/1 = on */
if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
- retval |= BIT(4);
+ retval |= RT_BIT(4);
/* bit5: 0 = drive 1 motor off/1 = on */
if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
- retval |= BIT(5);
+ retval |= RT_BIT(5);
#endif
/* DMA enable */
retval |= fdctrl->dma_en << 3;
--- VirtualBox-1.5.2_OSE/src/VBox/Devices/Storage/VDICore.h.2.6.24 2007-08-30 17:16:22.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/Devices/Storage/VDICore.h 2007-12-03 12:07:19.000000000 +0100
@@ -421,9 +421,9 @@ DECLINLINE(PRTUUID) getImageParentModifi
/**
* fModified bit flags.
*/
-#define VDI_IMAGE_MODIFIED_FLAG BIT(0)
-#define VDI_IMAGE_MODIFIED_FIRST BIT(1)
-#define VDI_IMAGE_MODIFIED_DISABLE_UUID_UPDATE BIT(2)
+#define VDI_IMAGE_MODIFIED_FLAG RT_BIT(0)
+#define VDI_IMAGE_MODIFIED_FIRST RT_BIT(1)
+#define VDI_IMAGE_MODIFIED_DISABLE_UUID_UPDATE RT_BIT(2)
/**
* Image structure
--- VirtualBox-1.5.2_OSE/src/VBox/Runtime/include/internal/thread.h.2.6.24 2007-08-30 17:16:24.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/Runtime/include/internal/thread.h 2007-12-03 12:07:19.000000000 +0100
@@ -132,14 +132,14 @@ typedef struct RTTHREADINT
* @{ */
/** Set if the thread is an alien thread.
* Clear if the thread was created by IPRT. */
-#define RTTHREADINT_FLAGS_ALIEN BIT(0)
+#define RTTHREADINT_FLAGS_ALIEN RT_BIT(0)
/** Set if the thread has terminated.
* Clear if the thread is running. */
-#define RTTHREADINT_FLAGS_TERMINATED BIT(1)
+#define RTTHREADINT_FLAGS_TERMINATED RT_BIT(1)
/** This bit is set if the thread is in the AVL tree. */
#define RTTHREADINT_FLAG_IN_TREE_BIT 2
/** @copydoc RTTHREADINT_FLAG_IN_TREE_BIT */
-#define RTTHREADINT_FLAG_IN_TREE BIT(RTTHREADINT_FLAG_IN_TREE_BIT)
+#define RTTHREADINT_FLAG_IN_TREE RT_BIT(RTTHREADINT_FLAG_IN_TREE_BIT)
/** @} */
--- VirtualBox-1.5.2_OSE/src/VBox/Runtime/r0drv/alloc-r0drv.h.2.6.24 2007-08-30 17:16:24.000000000 +0200
+++ VirtualBox-1.5.2_OSE/src/VBox/Runtime/r0drv/alloc-r0drv.h 2007-12-03 12:07:19.000000000 +0100
@@ -42,11 +42,11 @@ typedef struct RTMEMHDR
/** @name RTMEMHDR::fFlags.
* @{ */
-#define RTMEMHDR_FLAG_ZEROED BIT(0)
-#define RTMEMHDR_FLAG_EXEC BIT(1)
+#define RTMEMHDR_FLAG_ZEROED RT_BIT(0)
+#define RTMEMHDR_FLAG_EXEC RT_BIT(1)
#ifdef RT_OS_LINUX
-#define RTMEMHDR_FLAG_EXEC_HEAP BIT(30)
-#define RTMEMHDR_FLAG_KMALLOC BIT(31)
+#define RTMEMHDR_FLAG_EXEC_HEAP RT_BIT(30)
+#define RTMEMHDR_FLAG_KMALLOC RT_BIT(31)
#endif
/** @} */
--- VirtualBox-1.5.2_OSE/Config.kmk.2.6.24 2007-10-18 14:16:17.000000000 +0200
+++ VirtualBox-1.5.2_OSE/Config.kmk 2007-12-03 12:07:19.000000000 +0100
@@ -674,6 +674,7 @@ ifdef VBOX_OSE
DEFS += VBOX_OSE
endif
+DEFS += _INTPTR_T_DECLARED
#
# Compiler optimization flags.
#
@@ -1204,7 +1205,7 @@ ifneq ($(filter linux,$(BUILD_TARGET)),)
kernelpath := $(VBOX_LINUX_SRC)
endif
ifeq ($(BUILD_TARGET_ARCH),x86)
- VBOX_LINUX_INCS += $(kernelpath)/include/asm-i386/mach-default
+ VBOX_LINUX_INCS += $(kernelpath)/include/asm/mach-default
endif
endif
endif
