Covered-Related NEWS
====================
* 10/24/2009
Stable release covered-0.7.7 made. This is a bug fix release only.
- Fixed compilation warnings when compiling on 64-bit Mac OS X and Debian-based platforms.
- Updates to build scripts to help downstream Debian releases builds.
- Fixed bug 2880705. $Id: keywords containing newlines are now handled properly. Additionally, fixing issues
with multiply instantiated modules within a generate block.
- Fixed bug 2881869. Fixed a stack overflow issue in the gen_item_resolve function that would cause segmentation
faults when too many items were being generated within a single generate block.
- Fixed bug 2882433. Fixed the "ERROR! Parameter used in expression but not defined in current module" error
when a generated module instance has a parameter override of a parameter with the same name as the parameter
within the module that contains the generate block.
* 8/24/2009
Stable release covered-0.7.6 made. This is a bug fix release only.
- Fixed misspelling in report generator code (misspelling showed up in text reports)
- Fixed issues with performing module merging with modules containing generate blocks configured differently
for different instantiations of the same module.
* 8/2/2009
Stable release covered-0.7.5 made. This is a bug fix release only.
- Fixed bug 2808818. If a generate variable name collided with a reg/wire name, Covered was not emitting an error.
- Fixed bug 2808820. If no signal was used from the dumpfile and at least one signal needs information from the
dumpfile, Covered needed to signal a user error.
- Fixed bug 2812321. Parameterized/generated modules could get incorrect coverage calculated for them.
- Fixed bug 2812495. Fixed a crash issue. There is another part to this bug report that is not fixed, however.
- Fixed bug 2813405. A design run with the -g score option caused the GUI to freeze when viewed.
- Fixed bug 2813948. Fixed assertion issue with merging scored and unscored CDD files.
* 6/17/2009
Stable release covered-0.7.4 made. This is a bug fix release only.
- Updated regression files for the new 2.4 version of the OVL.
- Fixed bug 2804585. Memory reads in LHS part selects were not being marked for memory coverage.
- Fixed issue with VPI usage in a VCS simulation with generate statements.
- Fixed bug 2805191. Automatic tasks/functions that manipulate variables outside of the task/function
can cause incorrect toggle coverage for those signals.
- Fixed bug 2806855. Generate blocks generating module instantiations could lead to score command
errors (segfaults, internal assertion errors, etc.)
* 6/4/2009
Stable release covered-0.7.3 made. This primarily fixes a few bugs in the compile of Covered "out of the box". It
seems that even with the regression testbench, things can still slip through the cracks :( Anyhow, please use this
release instead of the 0.7.2 release.
* 5/29/2009
Stable release covered-0.7.2 made. This is primarily a bug fix release with a few new features added to the CLI. Here
are the details of the changes.
- Fixed bug 2791651. Memory deallocation errors occurred when syntax errors were being reported by the parser.
- Fixed bug 2791599. Whitespace prior to a `line or #line directive were not being handled properly.
- Fixed bug 2794588. If a module was specified in a -v option after its directory was specified by the -y option
to the score command, the module was not found for parsing.
- Fixed bug 2794684. If a normal (not generate) case statement within a generate block will output the case expression
to be output to the CDD more than once, leading to internal assertion errors when the CDD file is read.
- Fixed bug 2795088. When a CDD file is opened from the wizard GUI window, the open file window can be placed behind the
wizard window. Instead the wizard window should disappear once a selection button has been clicked.
- Fixed bug 2795086. If the user clicked on the global exclusion reason listbox when it is empty, a Tcl/Tk error message
box was raised.
- Fixed bug 2795089. If the GUI detailed combinational logic window is used to view several expressions one after the
other, Covered can segfault.
- Fixed bug 2795583. Score command segfaults when a module is instantiated within a generate block and overrides a
parameter value within the module.
- Fixed bug 2795640. Variables instantiated within a generate block caused issues with Covered when simulated with VCS.
- Fixed bug where memory elements being assigned via non-blocking assignments were not being evaluated, leading to
incorrect coverage output.
- CLI updates/fixes:
- When the 'debug on' command is specified, a line specifying that the debug mode is now on is output (previously
nothing was output (because the debug mode was off).
- Changed the 'debug on' command to 'debug less' and 'debug more' where the prior only outputs the executed statements
and timestep information during simulation while the latter outputs what 'debug on' used to output (extremely verbose).
- Fixed bug 2795209. When an unknown CLI command was specified, a memory error occurred.
- Fixed bug 2795215. Status bar was attempting to be output during simulation when debug mode was turned on. This
created some unreadable/messy output.
- Changed the 'goto <num>' command to 'goto time <num>'.
- Added 'goto line [<filename>:]<num>' command which simulates until the specified line number is about to be simulated.
- Added 'goto expr <signal> <bool_op> <value>' command which simulates until the given expression evaluates to
a value of true.
- Added support for handling the Ctrl-C interrupt when the score command is simulating with the -cli option specified.
In this case, simulation will immediately stop and return a CLI prompt which will allow the user to continue interacting
with the simulation.
- Updated user guide documentation to include the changes made to the CLI.
* 5/7/2009
Stable release covered-0.7.1 made. This is a bug fix release only. Here are the details:
- Fixed bug 2782473. CDD files being merged from different testbenches but with similar leading hierarchy
(but different top-level modules) which would lead to internal assertion errors.
- Fixed bug 2785453. Wires declared in generated named scopes were not handled correctly by Covered in VPI mode of operation,
leading to inaccurate coverage information.
- Fixed bug 2786986. An always block with a part select in the sensitivity list was triggering on the entire signal change
rather than the specific part select, leading to a potential degradation in performance and inaccuracy in coverage information.
- Allow time variable types to be included for coverage.
- Fixing permission issue with the install-sh script that some people would get after first downloading and installing.
- Updated README and INSTALL files to be more accurate.
- Fixed coverage accuracy issue for code that uses variable part selects in LHS of expressions.
* 4/26/2009
Stable release covered-0.7 made. This description contains only the changes made between the 11/19/2008 and this release.
This is primarily a bug fix period. Here are the details:
- Added many new diagnostics to help with C source code coverage.
- Fixed memory leak issue when profiling output is directed to unwrittable file.
- Fixed bug 2423290. Arithmetic right shift operator was not acting like a logical right shift operator when
the left operand was an unsigned value.
- Fixed bug 2471776. The $time system call was not returning the correct value if the timescale was not 1-to-1.
- Fixed bug 2482797. If an unpacked dimension is accessed for a memory read, memory read coverage is not output
correctly (not reported as being read).
- Fixed bug 2446877. Big endian signals were not being handled correctly from the VCD file.
- Fixed bug 2502095. Named blocks within generate statements generating wrong code.
- Adding support for line order reporting when included files contain coverage information.
- Fixed bug 2562345. Timescales were not being handled properly in a DOS-formatted file.
- Fixing issue where text following an `ifdef, `ifndef and `elsif was being parsed incorrectly.
- Fixed bug 2565447. Added support for LAND and LOR "static" operators to allow these operator types to be used
in generate blocks.
- Fixed bug 2565347. Added missing support for $signed and $unsigned system function operators.
- Fixed issue where a user-defined system call is found in the logic and Covered issues an error message.
- Fixed bug 2565259. Fixed a bug with preprocessor's handling of `include filenames.
- Fixed bug 2565405. Signed input/output signals were not parsed correctly.
- Fixed bug 2422415. Fixed simulation/coverage issue with comma-separated case items.
- Fixed bug 2614516. Added support for != operator in "static" expressions.
- Fixed bug with obfuscation global option.
- Fixed bug which produced segmentation fault when the $Id: NEWS,v 1.55.2.8 2009/10/25 04:31:42 phase1geo Exp $ keyword is found in a Verilog source file.
- Fixed bug 2617354. Fixed parameter handling in generate blocks.
- Added capability to ignore race condition checking on a per-module basis. Enhanced the -rI option to allow an optional
module name (i.e., "-rI=foobar") to be specified to achieve this functionality.
- Updated user documentation
- Cleaned up all splint warnings
- Fixed bug 2722062. When an error is found within a Covered command run, Covered will now return a value of 1 (EXIT_FAILURE)
instead of a value of 0.
- Fixed bug 1899674. When the score command is run to perform VCD scoring (after the CDD file was created with the score command)
and the CDD file was found to be empty, an internal assertion error was output instead of a readable user error message.
- Fixed bug 2779785. Segmentation fault occurred when reporting certain Verilog styles (error in code generator).
- Fixed bug 2781023. Segmentation fault occurred when reporting certain Verilog styles (error in combinational logic
underline functionality).
- Performed various non-functional code cleanup.
* 11/19/2008
Development release covered-20081119 made. This development release adds support for more complex CDD merging (previously
only CDDs with the same DUT hierarchy could be merged). Now different (including overlapping) blocks from different
parts of the design can be merged together as well as shared modules from different designs. Includes a few bug fixes and
documentation updates for the merge command. The following is a list of the changes that went into this development release.
- Added new merge capabilities that allow two or more CDD files with different top-most scored modules to be merged
together. Also added ability to merge two similar modules from different designs.
- Fixed bug 2223054. Remove false positive combinational logic cases when non-zero values are within concatentations ({})
and conditional expressions (?:).
- Fixed bug 2253402. Removed help_wrapper.tcl sourcing in Tcl/Tk scripts (this file was removed in the covered-20081030
development release).
- Fixed bug 2311710. Segfault would occur if a combinational logic expression was excluded/included via the GUI when
in instance reporting mode.
- Updated merge command documentation to describe new merging capabilities in User's Guide.
- Enhanced the configuration scripts to work with new versions of Icarus Verilog (include files for IV moved to a new
location). These changes should be backward compatible for older versions of IV.
- Added several new diagnostics to regression suite to verify new functionality.
Note that CDD files generated with this version of Covered will not be backwards compatible with previous versions of
Covered. This development release marks the last of the feature additions that will go into the upcoming 0.7 stable release
of Covered. This branch is now in feature freeze and only bug fixes, regression updates and documentation changes will go
into this branch. You may consider this development release to be a beta version of the 0.7 stable release due to be released
later this year.
* 10/30/2008
Development release covered-20081030 made. This development release is primarily a language support release in that
now Covered handles real numbers and has support for several built-in system task/function calls. A few bug fixes
have also been included along with documentation updates. Here's the rundown of the changes:
- Fixed bug 2158297. When initialized registers are output in a coverage report, a segmentation fault occurred.
- Fixed bug 2158626. Initialized registers could report missing toggle coverage information in several instances.
- Removed register initialization statements from line coverage.
- Added full support for real numbers (real, realtime and shortreal) as both mathematical values as well as delay values.
- Added support for runtime plus arguments to score command (also added the ability to specify plusargs to the New CDD
creation wizard in the GUI).
- Added functional support for the following built-in system task/function calls: $bitstoreal, $bitstoshortreal, $rtoi,
$test$plusargs, $itor, $value$plusargs, $shortrealtobits, $realtobits
- Added the ability to allow the following built-in system task/function calls such that logic blocks containing these
will now be able to be considered for coverage: $swrite, $dumpports, $ferror, $swriteb, $dumpportsall, $fflush, $swriteh,
$dumpportsoff, $fgetc, $swriteo, $dumpportson, $fgets, $dumpportslimit, $ungetc, $dumpportsflush
- Outputs an error if the value specified for the -P option to the score command is specified incorrectly.
- Fixed timescale issues
- Fixing time 0 problems for VPI mode of operation
- Fixed toggle coverage results for automatic functions/tasks.
- Updated User Guide per these changes
- Enhanced regression suite to verify new functionality.
* 10/07/2008
Development release covered-20081006 made. This development release is both a feature and a bug fix release. The main
feature additions include a new "exclude" command which allows the user to exclude coverage points from the command-line
and provide (optional) reasons for the exclusion which are saved in the CDD file and can be output in reports. Exclusion
reasons can also be specified now using the GUI. Additionally, support for the $time, $random, $urandom, $urandom_range
and $srandom system functions are provided along with handling of several system tasks (see User's Guide for a detailed
list of supported system tasks/functions) such that logic blocks containing these will not be automatically excluded from
coverage consideration. The following is a detailed list of the changes that has gone into this development release of
Covered.
- Added a new "exclude" command which allows coverage points in the design to be excluded (with an optional exclusion
reason provided)/included. You can also display the current exclusion status and reason for a given coverage point using
this command.
- Added a new -x option to the report command that will display the exclusion ID for the various coverage points that
is used for excluding/including coverage points via the new "exclude" command.
- Added a new -e option to the report command that will display excluded coverage points and their reasons for exclusion
to the report file.
- Added ability in GUI to create generic exclusion reasons in the Preferences window which can be used when providing
exclusion reasons in the GUI for common exclusions.
- Added ability in GUI to provide exclusion reasons when excluding a coverage point.
- Fixing issue with the use of the kfmclient for help viewing (KDE).
- Fixed bug 2095796. When the root expression in the verbose combinational logic window is excluded, the highlight colors
were not changing to indicate that the line is "covered".
- Fixed bug 2095799. When a memory element was excluded, the colors in the verbose memory window were not adjusted to indicate
that the memory was "covered".
- Updated covered.spec (RPM build file) to match current state of Covered.
- Fixed bug 2104947. Missed indexed memory operations are not output in the report file correctly.
- Fixed bug 2104924. Indexed memory operations were not emitting correct coverage information in combinational logic coverage.
- Fixed bug 2106313. The !== operation result was not correct.
- Cleaned up splint warnings in source code.
- Fixed bug 2112858. "Multi-tiered" merging was not reporting the correct contributing coverage files.
- Fixed bug 2112509. Support added to merge files with the same basename but different directories (relative pathnames are used).
- Fixed bug 2112613. Multi-expressions that were marked to be excluded were output in the report files as both excluded
and uncovered.
- Fixed memory issues with obfuscation code and made minor performance enhancements with this functionality.
- Fixing issue with rank command when an invalid option was specified (output incorrect output message previously).
- Added module version parsing support to parser. If this information is specified in an $Id..$ string within a comment,
it is extracted and saved in the CDD.
- Fixed bug 2122019. Added documentation for the -m option to the score command.
- Added new -er option to the merge command which specifies how to resolve exclusion reasons that are specified for the
same coverage point in two CDD files that are being merged. See user guide for more information.
- Added new "Merging" preference pane to GUI that allows the user to specify how the GUI will resolve exclusion reasons when
reading and merging in CDD files (much like the -er option to the merge command).
- Fixed bug 2123730. Error in parsing unsized constants (i.e., 'h0) in some instances (ex. "assign a = #1 'h0;").
- Fixed bug 2123300. Toggle and FSM coverage points are not properly merged.
- Fixed bug 2124635. If the current GUI metric state is set to "Toggle", no opened files exist and a preference change causes
an error to occur stating that the current functional unit could not be found.
- Fixed bug 2125451. Fixed VPI usage errors.
- Fixed bug 2127185. An "if" statement with an empty true scope caused a segmentation fault.
- Fixed bug 2127678. Fixed assertion error in db_close function when LXT2-style dump scoring.
- Fixed bug 2127687. Fixed memory leaks when using the LXT2-style dump scoring.
- Fixed bug 2129623. X values between 0/1 values should not impede on toggle coverage (i.e., 0->X->1 should be considered as a
toggle from 0->1 while 0->X->0 is treated as no toggle change (conservative approach)).
- Fixed bug 2133113. Error message displayed when Konqueror browser is used to view help information.
- Created new banner graphic for Covered and integrated this into the GUI.
- Fixed bug 2136474. An internal Covered error was displayed when forever blocks were used within fork..join.
- Fixed bug 2127674. LXT-style dump information in documentation should have been specified as LXT2 (LXT not supported).
- Fixed bug 2127694. Task/function port handling caused errors in some instances.
- Adding functional support for the $time, $random, $urandom, $urandom_range and $srandom system functions.
- Adding coverage handling support for $dumpall, $dumpfile, $dumpflush, $dumplimit, $dumpvars, $dumpoff, $dumpon, $fdisplay,
$fmonitor, $fstrobe, $fwrite, $history, $key, $list, $log, $monitor, $monitoroff, $monitoron, $nokey, $nolog, $printtimescale,
$showscopes, $showvariables, $showvars, $strobe, $timeformat, $write, and $fclose.
- Added -conservative option to the score command to force Covered's parser to remove logic blocks from coverage consideration
if they contain code that could potentially lead to coverage inaccuracies.
- Added -Wignore option to the score command to suppress warning information from output.
- Fixed bug 2124669. When multiple files are opened simultaneously in the GUI, no design output was displayed in the GUI.
- Fixed bug 2131171. If a block is removed from coverage consideration, no warning message was output to indicate that this
was being done and why.
- Added -dumpvars option to the score command which will generate a top-level module that will contain the necessary $dumpfile
and $dumpvars calls to most effeciently gain coverage for a design that is being scored via a VCD/LXT2 dumpfile. See
the User's Guide for more information.
- Added the support for the -dumpvars option to the GUI new CDD creation wizard.
- Deprecated the -vpi_ts option to the score command. This option is now called -top_ts and can be used with either the
-vpi or -dumpvars options.
- Added lots of new diagnostics to the regression suite to verify new functionality and to improve code coverage in
Covered's source code.
- Updated necessary documentation in User's Guide and manpage.
Note that the CDD version numbers have changed in this release, making them incompatible with CDD files created from older
versions of Covered.
* 8/26/2008
Development release covered-20080826 made. This development release contains several new features, bug fixes, GUI
enhancements and additions, documentation overhaul and testsuite enhancements. One major feature is the new "rank"
command which allows you to specify multiple CDD files to it and it will select an "optimal" subset of CDD files
needed to achieve the same amount of coverage that all of the files together provide, ranked in the order that these
CDD files should be run in simulation to achieve the most coverage in the fastest amount of time. A big thanks to
Ed Spittles (ed.spittles@gmail.com) for his recommendation and insight for this feature. I think you'll like what
you see as the time for a new stable release draws nearer (I'm planning on an end-of-the-year release date for the new
0.7 stable release). As you can see, Covered development has been very busy since the last development release.
Please give this a try and report those bugs! Here's a list of the changes going into this work:
- Fixed bug 1980954. Single-bit expression elaboration could lead to segfault.
- Fixed bug 1981073. Parameterized port specified twice (once with port direction, once with type specification)
lead to a memory leak.
- Fixed bug 1982530. The empty string "" was not being handled correctly, leading to a segfault.
- Added full support for the use of NULL statements ";"
- Added configuration checks for the lex (flex) and yacc (bison) code generators.
- Added many new diagnostics to cover holes in the regression suite as found by performing C source code coverage.
- Added a new "rank" command (there are now four main commands to Covered) which allows multiple CDD files to be
ranked in terms of coverage gained. Generates a report specifying its results and correlating coverage statistics.
- Has the ability to show which CDD files are unnecessary in terms of adding new coverage information. This
reduction capability allows users to reduce the size (runtime) of their regressions.
- Ranks the "needed" list of CDD files in the order that their simulations should be run (in terms of regression).
This information can be useful for creating "quick" regressions that need to hit as much logic as possible (but
not necessarily all) in a relatively short period of time for the purposes of design change confidence.
- Has the ability to allow user's to specify a list of CDD files that MUST be included in the final list of CDDs
to run.
- Added -f options to all of the commands (previously, only the score command had this option) which allows a file
to be specified containing more command-line options.
- Fixed some issues pertaining to -m32 compiler option support (on 64-bit systems).
- Fixed bug 1986510. The compiler error message "lxt2_read.c:1394: error: extended registers have no high halves"
when compiling with the -O3 option to the 4.1.x (and later) GCC compilers.
- Added ability to create/run regression tests using a perl script (rather than only via Make rules).
- Fixed segmentation fault when the global -D option was specified and the input CDD file was empty.
- Fixed bug 1997423. If a fully covered signal was output in toggle coverage when the -c option is specified to
the report command, the signal was not being output.
- Cleaned up all -Wall GCC warning messages.
- Fixed bug 1994896. Array overflow condition in new vector code causing segfaults.
- Optimized --enable-debug enabled code (runs almost as fast now as without the --enable-debug mode).
- Reduced the number of files in the regression directories.
- Fixed bug 2000732. Valgrind reported error in new vector code.
- Fixed memory leak issue for command option files that contain environment variable references that are not set
in the environment.
- Fixed bug 2001894.
- Fixing splint and GCC -Wextra warnings/errors.
- Added -m option to the score command which allows the user to specify a message to be associated with a created
CDD file (the contents of this message can be most anything -- the information is currently not being used by
Covered but may in the future).
- Added -d and -ext options to the merge command (these options exist in the rank command as well) to allow the
user to specify a directory and extension to use for finding CDD files to merge.
- Fixed CDD file format to remove memory allocation errors when many CDD files are merged into a single CDD file.
- Fixed bug 2054686. Toggle, memory and combinational logic coverage points within an unnamed block were not being
reported in the GUI and ASCII reports.
- GUI changes
- Refreshed the look of the GUI, replacing many widgets with better/newer widgets. The GUI is now reliant on
Tcl/Tk versions of 8.4 (preferable 8.5) and newer (it used to be backward compatible to 8.3).
- Replaced most of the listbox widgets with the new tablelist widget (this new widget needs to be downloaded and
installed in the user's Tk library prior to using Covered's GUI).
- Added a "general" pane to the preferences window that allows the user to modify general components of the GUI.
- Added a starting "wizard" window that pops up on startup to allow the user to quickly do various tasks. This
window can be turned off via a checkbutton in its window and/or the general preferences pane.
- Added the ability to create new CDD files from the GUI (rather than having to use the command-line score
command) via a new "New CDD Creation" wizard accessible from the File > Generate menu (or from the new
wizard window).
- Ability to create a score command option file from the GUI after options have been selected (this file can
be loaded by later references to the New CDD Creation wizard and/or the -f option to the score command.
- Added the ability to rank two or more CDD files from the GUI (rather than having to use the new command-line
rank command) via a new "Rank CDDs" wizard accessible from the File > Generate menu (or from the new wizard
window).
- Ability to create a rank command option file from the GUI after options have been selected (this file can
be loaded by later references to the Rank CDDs wizard and/or the -f option to the rank command.
- Ability to use currently loaded CDD files in the GUI to the rank list.
- Includes the ability to view this generated report file directly in the GUI via a new file viewer window.
- Reworked the entire ASCII report generation functionality to work as a wizard window (like the New CDD and Rank CDDs
wizards). Removed "ASCII Report Options" pane from the preferences panel. This feature is accessible via
the File > Generate menu option.
- Ability to create a report command option file from the GUI after options have been selected (this file can
be loaded by later references to the ASCII Report Generation wizard and/or the new -f option to the report
command.
- Added ability to view this file information directly in the GUI via a new file viewer window.
- Fixing memory errors when Tcl/Tk script fails/errors.
- Fixed bug 1989398. Toggle coverage results were not being
- Added support for tooltips to many of Covered's widgets. Tooltips can be turned on/off in the preferences
window.
- Added ability for GUI to remember window placements, tablelist column sizes/positions/states and other miscellaneous
state information while it is being used and, optionally, between application uses. The ability to remember
this information between application runs is configurable in the preferences window.
- Added full support for instance-based coverage accumulation in the GUI. The user can now select either mode
in the GUI and get immediate results. Additionally, coverage exclusions are transferable between modes (excluding
a coverage point when in module mode will exclude all instances, but excluding a coverage point in an instance will
only exclude the module coverage information if all instances of that module are excluded).
- Updated the Next (-->) and Previous (<--) buttons in all windows to use new graphical buttons.
- Updated the search widgets to use a more graphical, modern approach.
- Fixed bug 2054689. In verbose combinational logic coverage window, when expression was excluded, the highlighted logic
did not change to hit colors.
- Fixed bug 2060873. Excluded subexpression was not outputting its coverage information in the lower window when later
selected.
- Fixed other various memory leak bugs in GUI.
- Switched user guide and GUI documentation from HTML and HTML help formats, respectively, to a single, unified document
in DocBook format. This ties all of Covered user documentation to a single set of source files for easier maintenance.
Removed support for HelpSystem in GUI.
* 5/30/2008
Development release covered-20080530 made. This development release is primarily a scoring optimization
release. The structures used for vectors was completely reconstructed to achieve 2-3x performance improvement
over the last development release. I am now seeing scoring runtimes that almost match those of Cver. A few
bugs were also fixed in this release. The following is a list of these changes.
- Fixed bug 1950946. If a value was supplied to the global -P option, the command-line parser got
confused and skipped the next option/command on the line.
- Fixing various memory deallocation issues when user errors are reported.
- Rewrote vector and expression operation functions to make use of more efficient coverage calculations.
- Coded vector structure to use unsigned longs to make best use of performance optimizations on current machines.
Added capability to vector read functions to be able to translate CDD files written by a 32-bit machine to 64-bit
format and vice-versa.
- Rewrote FSM arc structure and functionality to improve performance of FSM coverage calculations. The new
structure also allows the input and output states to be of different bit widths.
- Added several new diagnostics to regression suite to improve Covered's internal code coverage and to verify new
code cases.
- Fixed bug 1966994. Merged coverage files were appending score command-line arguments to the new CDD file which
created memory allocation problems and unnecessarily increased the size of the CDD file.
- Fixed bug 1965927. Multi-line defines were causing problems with line numbers in reports.
- Fixed bug 1979698. Embedded, empty begin..end block causes top-level block to be diregarded from coverage
consideration.
This is a substantial improvement in speed, so please give it a try and please report any bugs that you may find.
* 4/15/2008
Development release covered-20080415 made. This development release contains several code optimizations,
memory leak fixes, and GUI improvements. The following is a list of these changes.
- Bug fixes from 0.6.2 stable release.
- Fixed all memory leak issues with regressions and added code instrumentation and some post-processing
scripts to automatically verify that there are no memory leaks for regression runs.
- Code reduction in parser
- Modified the way that vectors were being assigned to fix memory leak issues with their deallocation.
- Optimized coverage accumulation during scoring in expression functions.
- Optimized unknown and not-zero factoring of vectors to improve scoring speed
- Added new diagnostics to regression suite to verify fix for LHS expression calculation
- Optimized vector operation functionality to improve scoring speed.
- Removed the LAST expression operator type (internally used type that is no longer needed due to the
optimization improvements)
- Updated several components of the GUI, including the module/instance listbox (now contains summary
information including hit, miss, total, hit percent and coverage color in background), removed the
summary window (no longer needed due to module/instance listbox change), substituted home-made
window resizing handles for Tcl/Tk 8.4/.5 panedwindow types, substituted "-->" and "<--" buttons for
graphical buttons to improve look, and several other aesthetic and functional changes.
- Fixed several issues/bugs with GUI.
Of particular note is that the CDD version is now incompatible with other versions of Covered. Also, I am planning
on only supporting the GUI for Tcl/Tk versions of 8.4 or newer (I used to support 8.3 but the Tcl/Tk homepage no
longer offers these older versions and I am taking advantage of some of the newer widgets available in these versions).
The GUI also requires that the tablelist (version 4.8) Tk widget be installed in the auto_path. Additionally,
the GUI documentation is not up-to-date with this release, but will be updated by the next development release.
Give the new performance improvements a try and be sure to check out the improved GUI report analyzer!
I am planning on working on some (hopefully) major improvements in performance to the score command for the
next development release as well as adding full support for instance coverage viewing in the GUI as well as
some advanced coverage merging capabilities that will allow the user to get graded test information as well!
As always, have fun and be sure to log those bugs!
* 3/14/2008
Development release covered-20080314 made. This development release contains a slew of new features,
score optimizations, bug fixes and documentation/regression updates/additions. The following is a list
of these changes.
- Bug fixes from 0.6.1 stable release.
- Added -ef option to score command to allow the user to exclude final blocks from coverage consideration.
- Added -ep option to score command to allow the user to pay attention to inline pragmas which allow the
user to exclude certain code from coverage consideration (more control than other -e? options).
- Fixed bug in toggle reporting where the exclusion property was not being handled correctly.
- Changed metric mode selection in GUI to a tk_optionMenu widget instead of using radio buttons (minimizes
this information in the GUI and makes it somewhat less confusing as to which mode of operation we are in).
- Added metric mode selection widget to summary window to allow the user to navigate all metrics in that
window alone (events are synchronized between the main window and the summary window).
- Fixed several aesthetic issues with the GUI running on Mac OS X.
- Removed exit() calls within the code and replaced them with an exception handling scheme using the
cexcept (http://cexcept.sourceforge.net) project. This allows us to much more cleanly exit in terms of
memory, file streams and temporary files.
- Added support for race condition embedded pragmas to allow the user to skip checking certain blocks of
logic (-rP option to score command).
- Removed for loop control assignments from race condition checking consideration.
- Added support for $finish and $stop system calls. These are handled correctly by the score command and
no longer cause blocks containing them to be excluded from coverage consideration on their merit alone.
- Optimized simulator which will become quite apparent for larger designs.
- Updated user documentation and man pages to match new features.
Please note that CDD files created by this development release will not be backwards compatible with other
releases of Covered -- generate new CDD files for merging/reporting with this version of Covered. Have fun
and let's see those bug reports!
* 3/14/2008
Stable release covered-0.6.1 made. Bug fix release only -- here are the stats:
- Fixed bug 1899711. Making reading from FIFOs allowable instead of just FILEs.
- Fixed bug 1899735. Line coverage does not pay attention to exclusion property in generated reports.
- Fixed bug 1899768. Fixed simulation segfault issue caused by an empty default case of a case statement.
- Fixed bug 1899674. Outputting meaningful error message when a read CDD file is found to be empty.
- Fixed bug 1898164. Fixing background colors of FSM states/arcs when preference colors are changed.
- Fixed bug 1914056. Fixing segmentation fault which occurred if the body of a task is the null statement.
- Updated regression suite per these changes.
* 1/30/2008
Stable release covered-0.6 made. This release has been finally made after almost a year since the last
stable release was made. Many coding improvements have been made for performance optimization and portability.
Better debug features have been added along with a host of bug fixes. Please check out the following list
for a high-level view of what has been added to this release since the last stable release.
- Added support for unnamed scopes and the ability to create variables within these scopes.
- Modified simulator memory handling to optimize performance.
- Added support for a CLI debugging environment when scoring simulations (only available if Covered is built with the --enable-debug option).
- Added accumulated summary coverage information to generated reports for each metric.
- Fixed some compilation warnings dealing with large static values being assigned to unsigned long long variables.
- Added the ability to simulate and get coverage for automatic tasks/functions.
- Added ability to read/write file sizes that extend beyond 2G in size.
- Added support for embedded type information within for loops (i.e., for( int i=0; ... )).
- Started adding const information to function input pointers that will not be modified (small performance enhancement that the compiler can take advantage of).
- Added initial parsing capability for structs/unions.
- Added built-in profiling facility to generate profiling reports of Covered's internal functions (useful for enhancing/fixing performance problems in commands)
- Added several performance enhancements to Covered's score command (achieved 8x speedup in one simulation)
- Added additional build support to get VPI libraries to compile on more architectures.
- Lots of bug fixes.
- Added "Debugging" section to user guide to document the usage of the CLI, verbose debugging output generator and profiler.
- Updated user guide and development documentation
- Enhanced regression suite
* 1/20/2008
Development release covered-20080120 made. This is primarily a bug fix release over the last development
release and also includes some enhancements to the CLI. Additionally, Covered has been run under splint
to remove some potential issues. This release is meant to be a beta testing ground for the upcoming 0.6
stable release as it gets a pre-0.6 release into the hands of the general public. Please report any bugs
found with this release as soon as possible so that I can get a 0.6 stable release available. The
following is a list of changes in this release:
- Fixed code to run splint clean with the -weak option as well as a reduced set of the -standard option
(the shell script in the src directory contains the command-line that was run with splint if you want
to know exactly which checks were performed/not performed with splint).
- Fixed several bugs and potential bugs in code found by the splint utility.
- Added capability of running in VPI mode on Mac OS X (Icarus Verilog works at this point).
- Fixed 'next' command in CLI to work as intended
- Added 'goto' command in CLI to allow the user to jump to a specific timestep
- Added 'expr' command in CLI to allow the user to view a given expression by its Covered ID and its
current state/value.
- Renamed several CLI commands to make them easier to remember and reduces amount of typing required.
- Added status bar for step, next and goto commands in CLI to help the user understand if/when
progress was being made by the simulator.
- Fixed bugs with regards to the '!!' command in CLI (this should now work as intended).
- Fixed bug 1875180 which would lead to incorrect simulation results and would possibly cause a
Covered simulation to go into an "infinite loop".
- Added new diagnostics to regression suite.
- Documentation updates per changes.
* 1/3/2008
Development release covered-20080103 made. This is primarily a bug fix and performance enhancement
release over the last development release of Covered with a few new feature additions.
The following changes are included in this release.
- Added support for embedded type information within for loops (i.e., for( int i=0; ... )).
- Started adding const information to function input pointers that will not be modified (small
performance enhancement that the compiler can take advantage of).
- Added initial parsing capability for structs/unions.
- Updated all trevorw@charter.net e-mail addresses to new phase1geo@gmail.com e-mail address.
- Fixed VCD parsing error (bug 1832592).
- Added built-in profiling facility to generate profiling reports of Covered's internal functions
(useful for enhancing/fixing performance problems in commands)
- Added several performance enhancements to Covered's score command (achieved 8x speedup in one
simulation)
- Added "Debugging" section to user guide to document the usage of the CLI, verbose debugging output
generator and profiler.
- Fixed bug 1858408. This bug occurred when using newer versions of the OVL as well.
- Fixed bug 1861986.
- Added new diagnostics to verify additional functionality.
* 9/6/2007
Development release covered-20070906 finally made. Several severe changes to support CLI-style
runtime debugging, unnamed scope handling, some resimulation optimizations, automatic function/task
handling, and lots of bug fixes have gone into this release. The following changes are included in
this release.
- Added support for unnamed scopes and the ability to create variables within these scopes.
- Modified simulator memory handling to optimize performance.
- Fixed bug 1688487: The writability check on a -o file was accidentally removing the file if it
previously existed
- Added support for a CLI debugging environment when scoring simulations (only available if Covered
is built with the --enable-debug option).
- Fixed bug 1698806: Function calls made within operations were causing those operations to not get
bit-sized correctly.
- Added accumulated summary coverage information to generated reports for each metric.
- Fixed some compilation warnings dealing with large static values being assigned to unsigned long long
variables.
- Fixed bug with handling embedded scopes within generate blocks.
- Added the ability to simulate and get coverage for automatic tasks/functions.
- Added ability to read/write file sizes that extend beyond 2G in size.
- Fixed bug 1709984: Adding ability to enter defined values inside of covered_fsm attributes (to
match the documentation).
- Fixed memory leak bug in parser code.
- Fixed bug 1687409: Memory allocation information at end of score command written as a 32-bit signed
value -- changed to an unsigned long long value.
- Fixed error output when Tcl/Tk fails in initializing the Tcl/Tk environment.
- Fixed bug 1788991: Memory corruption bug due to memory (multi-dimensional array) accesses.
Lots of somewhat major changes to the simulation core and elaboration code have been made (hopefully for
the better). This development release is a springboard for adding further SystemVerilog support for some
other features of the language. Have fun and let's log those bugs!
* 12/05/2006
Development release covered-20061205 made. A few updates to the core code to properly support VPI
usage were necessary which is why this is not a stable release. At this point, regressions are fully
passing with Icarus Verilog, Cver and VCS in both dumpfile and VPI modes of operation -- an important
milestone for the upcoming 0.5 stable release. There is still additional testing of existing
functionality that needs to be done as well as finishing the GUI documentation support using the new
HelpSystem documentation reader utility before I would consider Covered ready for a new stable release.
The following changes are included in this release.
- Updated User Guide documentation to complete the list of score command options, document the -b
option to the report command, and include a FAQ item that addresses the question of the difference
between the stable releases and development releases.
- Updated regression Makefiles to allow testing of VPI, LXT and VCD modes of operation.
- Added Cver runs to regression Makefiles
- Started integrating the HelpSystem 1.5 Tcl/Tk widget into Covered's GUI to allow better and faster
documentation browsing for GUI information.
- Updated parser error output to make it easier to read.
- All bug fixes contained in the 0.4.8 stable release were applied to this release.
- Fixed bugs 1589519, 1589524 and 1589546 which are related to parser errors with the "signed" keyword.
- Fixed bug 1590104. A more meaningful error message is displayed if the -i option to the score
command is misused (or not used when it should be).
- Fixed bug 1599869. Uncovered "disable" statements are now handled properly by the report command.
- Lots of fixes to the VPI code were made as well as the core simulator to support correct behavior
when running in this mode, including:
- Added proper support for delay queueing
- Added 64-bit time support to core (originally this was just 32-bit).
- Added complete support for `timescale directive handling.
- Added -vpi_ts option to score command-line to allow the user to specify a timescale for
the generated top-level file created for VPI usage.
- Added support for time and integer types to make cbChangeValue callbacks.
- Added configuration support for detecting 8, 16, 32 and 64-bit types.
- Removed the usage of the iverilog-vpi script to create the Covered VPI module for Icarus Verilog,
using a normal call to the linker to create the appropriate shared object (allows for debug output
to be used in this mode).
Consider this development release to be a 0.5-beta release. If all goes well, the next release should be
the new 0.5 stable release! As always, have fun and log those bugs!
* 10/20/2006
Development release covered-20061020 made. The major additions in this release is the support for
memories/multi-dimensional arrays and bitwise coverage support. Associated with this functional
support, I have also created a new memory coverage metric that is available for usage in both the
report command as well as the GUI. Memory coverage currently answers the following questions about
a given memory:
1. What entries in the memory were written?
2. What entries in the memory were read?
3. What is the toggle information for each entry in the memory?
I plan to add a few more coverage points to memory coverage including: where any entries read before
they were written? and where any entries written and read simultaneously? However, I am open to more
ideas on memory coverage information that people would like to see. Read the accompanying User's Guide
and GUI User's Guide for more information on memory coverage and how to understand the coverage output
from both the report command and GUI. The following is a list of changes made from the last development
release.
- Fixed bug in code that removes statements from coverage consideration that were created by a
generate block.
- Fixed bug in race condition checker for generated items
- Fixed bug with multiply-and-assign (i.e., a *= b) operation
- Fixed bug in gen_item_resolve function where an instance was incorrectly being placed into a new
instance tree.
- Fixed parsing bug when a named begin/end block was empty
- Fixed bug in statement removal algorithm and optimized this process significantly
- Fixed several memory leak issues
- Added support for bitwise coverage information for vectored combinational expressions (i.e., given
the following code:
reg [3:0] a, b, c;
always @(posedge clock) c <= a & b;
You can get combinational logic coverage detail that would be equivalent to:
always @(posedge clock)
begin
c[0] <= a[0] & b[0];
c[1] <= a[1] & b[1];
c[2] <= a[2] & b[2];
c[3] <= a[3] & b[3];
end
This information is attainable using the new -b option to the report command.
- Adding parsing support for SystemVerilog "program" blocks (the contents within these blocks are ignored
for coverage purposes).
- Added support for SystemVerilog "final" blocks
- Updated GUI syntax highlighter to match all of the keywords that are currently detectable by the lexer
- Cleaned up extraneous comments from diagnostic Verilog files (should make the diagnostic tarball quite
a bit smaller).
- Added full parsing and handling support for memories and multi-dimensional arrays
- Added memory coverage metric to report command and GUI viewer
- Documentation updates to all user documentation for changes related to this release
- Fixed missing images in User Guide
- Added parsing and handling support of increment and decrement operators (both ++a and a++ varieties)
within expressions (i.e., if( a++ == b ) ...)
- Added proper support for the "wait( ... )" statement
- Optimized VPI version of Covered which should cause simulators to run faster than previously when interacting
with Covered through its VPI.
- Fixed bug with posedge and negedge handling within Covered to make it completely compliant with the LRM
(previously X->1 or Z->1 would not cause a posedge event to trigger and likewise for the negedge)
- Fixed several linking errors with the VPI library
- Added parsing support for unpacked arrays of non-registers for SystemVerilog enabled modules
- Fixed segmentation fault issue that occurred with generate blocks
- Fixed most compiler warnings (when using the -Wall operation to the compiler)
- Fixed bug with generating instances
- Fixed bug when merging two CDD files that contain full hierarchy
- Increased maximum bit width of signals from 1024 bits to 65536 bits
- Removed pragma comment parser from preprocessor as these are handled by the actual parser
This development release can be considered the beta release to a 0.5 stable release. The development
branch will be mostly in "feature freeze" mode at this point. Only bug fixes, documentation updates and
testing updates will be performed until we snap the new stable release. So give this version a try and
log those bugs!
* 09/04/2006
Development release covered-20060904 made. This is primarily an enhanced language support release
containing support for the Verilog-2001 'generate' block and support for some SystemVerilog constructs.
All bug fixes from the stable release branch have also been included in this release as well. Some
updates to the GUI (to match changes made on the score command side). The following is a list of
changes made from the last development release
- Complete parsing/simulation support for generate blocks include generate for, if/else and
case constructs.
- Fixed bug in hierarchically referencing items within an array of instances.
- Added -g option to score command to allow the user to specify on either a global or modular
level which Verilog generation to consider for that design. This allows a block of logic written
with Verilog-1995 in mind to use names that would be keywords in Verilog-2001 or SystemVerilog,
as an example.
- Removed "manstyle" type documentation in user's guide as this tool is no longer used for this
project. This change should be transparent to the user, however.
- Fixed scoping/hierarchical referencing rules to match the Verilog LRM properly.
- Added parsing/handling support for SystemVerilog always_comb, always_ff and always_latch blocks.
- Added parsing support for 'unique' and 'priority' SystemVerilog keywords before if and case
statements (Covered doesn't need to do anything with them, however).
- Added parsing/handling support for 'do .. while' SystemVerilog loops.
- Added parsing/handling support for new SystemVerilog data types, including: byte, bit, logic,
char, shorting, int and longint.
- Added -rI option to the score command which allows the user to completely bypass the race
condition checking phase of the score command.
- Added -B global option which obfuscates all identifying names from Covered's output (for use
in providing debugging information to the developer's of Covered).
- Added parsing/handling support for operate-and-assign SystemVerilog operators, including:
+=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=, ++ and --. These can be used wherever
their counterparts can be used (including generate for loops).
- Added proper handling of Verilog-1995 delayed blocking assignments (i.e., "a = #5 b;" or
"a = @(posedge clk) c;"). Previously, the delay was being incorrectly ignored which could
have lead to infinite looping of always/forever blocks or could calculate incorrect coverage
information.
- Added parsing support for SystemVerilog .name and .* port lists.
- Added partial parsing/handling support for SystemVerilog 'typedef' usage. This should work for
enumerations but not other data types at this point.
- Added parsing/handling support for SystemVerilog 'enum' constructs. These should be fully
supported with the exception of their built-in '.first', '.last', '.next', '.prev', '.num' and
'.name' methods.
- Added full support of handling Verilog-1995 repeated delay blocking assignments (i.e.,
"a = repeat(5) @(posedge clk) b;". These were previously being treated as normal blocking
assignments.
- Added keyword highlighting support in GUI for Verilog-2001 and SystemVerilog keywords depending
on the -g value specified for a particular module.
- Added parsing support for SystemVerilog assertion, property and sequence blocks. These constructs
are ignored by the parser but should not cause a parsing error now.
- Added parsing support for SystemVerilog multi-dimensional arrays. These are ignored by the
parser but should not cause an error.
- Added full support for the SystemVerilog $root global space -- though limited testing has
been performed with this at this point.
- Added -s option to the report command to suppress the output for modules/instances that contain
no coverage information.
- Updated all user documentation to match changes made for this development release.
- Lots of new diagnostics added to regression suite to verify the majority of these changes.
There you have it. A lot of enhancements made for language support for Verilog-1995, Verilog-2001
and SystemVerilog. Some of the additions for SystemVerilog, especially typedefs and $root global
space, have not been fully verified to work and may still be a bit buggy, but everything else should
be expected to work as advertised. Please submit any bugs that you find. The next development
release should contain support for some more language enhancements, including full support for
typedef and enumeration usage, support for memories, multi-dimensional arrays, structs and unions.
I will also be looking at adding support for bitwise coverage information (for vectored calculations).
As always, have fun!
* 07/08/2006
Development release covered-20060708 made. This new development release for the future 0.5 stable
release contains several enhancements to the GUI. The primary differences are the changes to the File
menu, the ability to exclude/include coverage cases for all metrics, and a new look for the preferences
window. See the following notes regarding GUI changes made.
- Added ability to open/merge more than one file at a time (only available if Tk version is >= 8.4)
- Added ability to save a changed/merged CDD.
- Added ability to close all opened CDD files so that new CDD(s) can be opened/merged regardless of
the design without needing to exit and restart the GUI.
- Added ability to generate ASCII reports from the GUI (includes the ability to set reporting options)
- Added ability to exclude/include coverage cases for all metrics
- Changed the look of the preferences window to be more tabular for purposes of minimizing desktop
space for this window even as the number of options increases.
- Added missing GUI elements to preferences window and summary window for assertion coverage
- Updated README file to inform where to find documentation for the GUI.
- Moved some VCS-only diagnostics to shared simulator diagnostic pool due to enhancements in IV
- Updated all GUI documentation and images to match the current state of the GUI.
- Added an RPM spec file to the CVS tree which will be used to generate RPMs for future stable releases
- Fixed bug in score command that caused a segfault when two or more signals were declared using
the same parameter in their range description (i.e., reg [FOO:0] a, b;).
The coverage exclusion/inclusion work is the primary reason for creating this development release.
All coverage information and GUI elements are automatically updated whenever a coverage case for a metric
is changed to either exclude it from coverage consideration or include it (because it was previously
excluded). The file menu changes were badly needed as well and are required to properly support the
exclusion/inclusion work (this allows exclusions to be saved/merged). Please report any bugs that crop
up in this area. Thanks!
* 05/30/2006
Development release covered-20060530 made. This new development release for the future 0.5 stable
release contains a lot of new features and enhancements over the 0.4.x releases. The changes are listed
below (Note: the major feature additions are noted with an asterisk (*)). Please note that all bug fixes
that were made to the stable releases (up and including 0.4.4) are included in this development release
as well.
* Added support for FSM coverage output in the GUI
* Added support for assertion coverage in the GUI and ASCII report mechanism
* Added Covered VPI module which can now allow Covered to score a design while the simulation is
executing (only the Icarus Verilog, Cver and VCS simulators are supported at this time).
* Added support to Covered merge command to merge two or more CDD files with one command (previously
only two CDD files could be merged at a time).
- Added support to allow coverage handling of blocks that contain the $display system call (previously
any block containing one of these system calls was disregarded for coverage).
- Added ability for Covered to automatically remove the need for OVL assertions when the "-A ovl" option
is not specified to Covered's score command.
- Added support for environment variable substitution in the configuration file that is passed to
Covered's score command with the -f option.
- Added support to allow Covered's GUI to be started from any directory and work properly (previously
Covered's GUI had to be started in the same directory as the design was scored from).
* Added syntax highlighting to all Verilog source code in the GUI (added support in Preferences window
to allow the user to specify different colors for the syntax highlighter).
* Causing all Verilog source code to be preprocessed before being displayed in the file viewer (fixed
bugs with defined values not being highlighted correctly).
- Updated all user guide, GUI and man documentation to match the current state of Covered.
- Added many new diagnostics to the test suite to verify the new functionality.
Lots of cool new features to give a go. You can consider these new features to be a beta version -- not
all features have been completely verified to work at this point. So please report any bugs that you find
with this new version. Have fun!
* 5/27/2006
Stable release covered-0.4.4 made. This release contains a bug fix to proper handle hierarchical
referencing of parameter values. This feature was technically not supported in the past but caused
an internal assertion error when this was performed. The feature is now fully supported.
* 4/21/2006
Stable release covered-0.4.3 made. This release contains a bug fix to the statement connection function that
caused segmentation faults during the score command. Also added support for big endian wires/regs. This
information was being ignored by the parser and, consequently, was not being handled correctly by Covered's
internal simulator, leading to incorrect coverage information. The lack of this support was also causing
an internal error in the memory allocation routine when scoring the dumpfile.
* 4/17/2006
Stable release covered-0.4.2 made. This release contains a bug fix that caused an assertion error in the
binding.c source file to occur. The reason for this assertion was a syntax error in the parser that caused
problems when more than one task call was made in a statement block. Also added support for multi-line
definitions (i.e., a '\' character used at the end of a definition line). This was missing but was not meant
to be missing.
* 4/4/2006
Stable release covered-0.4.1 made. This release contains one bug fix that causes an assertion error when
compiling designs that use a concatenation operation on the left-hand-side of assignment statements. If
you are experiencing this problem with the 0.4 release, it is recommended that you use this new release
instead.
* 3/29/2006
Stable release covered-0.4 made. In addition to all of the features, optimizations and bug fixes
that have gone into the development releases from the 0.3 stable release, the following features, updates
and bug fixes have been added.
- Fixed bug with a statement connection issue that causes lines of code to be not considered for
coverage that should have been.
- Fixed bug in report command where combinational expressions were not being output to match the original
Verilog code.
- Added CDD file viewer window to GUI to allow the user to see which CDD files are currently loaded/merged.
- Fixed bug in combinational logic verbose viewer which caused the window to resize dependent upon
the location of the cursor (this was an annoyance)
- Changed the output of simple combinational logic to change to unary combinational logic output if either
the left or the right expression was a constant value (eliminates unachievable combinational logic cases
from being output leading to more accurate coverage results).
- Removed combinational expressions that contain only constant values from being considered for coverage.
- Updated simple combinational logic output in reports to be as concise as possible for AND and OR type
expressions.
- Removed duplication of information in CDD files for race conditions.
- Fixed bug in GUI dealing with showing race conditions
- Fixing bug in GUI pertaining to the next/previous buttons in the combinational logic detail viewer. Previously,
clicking on one of these buttons would only advance you to the next uncovered line. Now it will advance
you to the next uncovered statement.
- Updated development, user and GUI documentation to reflect the above changes and to bring them up-to-date
with the rest of the tool.
Please see the ChangeLog file for all changes made from the 0.3 stable release to the 0.4 stable release.
Lots of enhancements, features, optimizations, bug fixes, performance improvements and documentation improvements
are contained in this stable release, making it very worth while for any Covered users to get their hands on
it.
* 2/18/2006
Development release covered-20060218 made. A lot of work has gone into adding a lot more Verilog-2001
support, added Verilog-1995 support, GUI improvements/fixes, user documentation additions/updates,
adding LXT dumpfile support and the usual bug fixes. I have also removed the diagnostic directory from
the Covered tarball and am making it available as its own tarball since it is growing by leaps and bounds
these days. The following is a list of the changes in this release from the past release.
- Added support for the following Verilog 2001 constructs:
- `ifndef, `elsif and `line preprocessor directives
- Constant function support
- Explicitly named parameter overrides
- Correct support for localparam
- Implicit (wildcard) sensitivity lists (@*)
- Support for signed values (integers are now treated as signed values) and proper handling of
signed expressions
- Immediate register assignment (ex. reg a = 1'b0)
- Variable multi-bit selects (ex. a[b+:10] or a[b-:2])
- Exponential power operator (**)
- Arithmetic shift operators (>>> and <<<)
- Inline parameters (i.e., parameters placed before a module port list)
- Inline port declarations (ex. module foo ( input wire [1:0] a, ... );)
- "Null" parameter overrides (ex. foo #(0,,2) bar (...);)
- Arrays of instances
- Added more support for attribute locations
- Added support for using LXT/LXT2 -style dumpfiles instead of just VCD files
- Fixing bug to properly bind to the appropriate task, function or named block when there
are two or more of this functional units with the same name.
- Changed all error information to get sent to stderr regardless of the output mode we are in
- Added left shift, right shift, exponential power, and constant function call operators to list
of valid operators to be used in constant expressions.
- Fixed bug for resolving parameter values that are used in tasks, functions or named blocks but
are not declared there (they are declared in the parent module).
- Added full support for hierarchical referencing
- Added full support for escaped names (ex. wire \some_name[0] ;)
- Added support for performing bit selection on RHS of parameter assignments
- Added full support for sizing parameters (ex. "parameter [2:0] foo = 0;")
- Fixed ASCII report output to display uncovered toggle signals in line order (this was inverted
for some reason).
- Fixed bug in score command-line parser to not segfault if file given in -f option is empty
- Fixed several bugs in GUI
- Added additional features for report GUI
- Added summary report window with ability to see modules/instances ordered by coverage
percentage for a given metric in either increasing or decreasing order (coverage information
is also color-coded to make it easy to tell which modules are "fully covered", "covered well
enough", or "not covered well enough").
- Added preferences window and removed preferences menu -- improved method of color selection
and added a coverage "good enough" selector used in the summary window
- Changed toggle coverage source code browser to only underline one instance of an uncovered
signal (this position is first implicit or explicit declaration of the signal) to improve
readability.
- Added configuration file read/write support for storage of Covered's preferences
- Added help buttons to toggle detail, combinational logic detail, preferences and summary window
to allow online help pages to be displayed for the current window
- Added GUI online help pages for toggle window, combinational logic window, preferences window
and summary window as well as updated all out-of-date information.
- Added navigational GUI elements to help the user find the next/previous uncovered line from any
window. Also added a search GUI element for finding any string in the source code window.
- Updates to user guide and development documentaiton to bring things up-to-date.
In summary, there have been lots of features added to both the score command and GUI report tool.
The CDD files generated from this release are not backward compatible with older releases. I plan
to make this version the next stable release once it has had some more test time applied to it.
So please submit those bugs!
* 1/9/2006
Development release covered-20060109 made. It has been almost a year since the last development
release of Covered, but in the meantime there has been a lot of work put into the score command
of Covered during this time to fix bugs, add more coverage support for various Verilog constructs,
simulate more accurately, remove memory corruption/estrangement and improve the run-time speed
of the score command. I think that user's of Covered will appreciate the enhancements. Documentation
updates have been made and build problems have been fixed (Covered now compiles cleanly for
Fedora Core 3 builds). I plan to revisit Covered's GUI in the next release to fix various bugs
and improve the usability. The following is a description of what has changed in this release from the
last release:
- Blocking assignments in covered blocks are now performed by Covered's simulation core instead of
being taken from the dumpfile to improve simulation/coverage accuracy.
- Fixed lots bugs with statement block removal
- Added patch to parser.y to fix compiling problems with bison-2.0.
- Increased space for module/instance name in reports
- Added full support for the following Verilog constructs:
- tasks and task calls
- functions and function calls
- named begin/end blocks
- fork/join
- event types and event triggers
- hierarchical referencing (both relative and top-of-tree scoping)
- initial blocks
- for, repeat and while looping
- block disabling
- Fixed bug with net_decl_assign statements (the line, start column and end column information was
incorrect, causing problems with the GUI output).
- Fixed implicit signal creation in binding functions.
- Fixed binding with merge command.
- Added --enable-debug configuration option to remove verbose outputting code from compilation.
This significantly improves run-time performance.
- Better race condition reporting
- Lots of fixes related to bad memory accesses and memory leaks (found using the valgrind utility).
- Removed Tcl/Tk from source files if HAVE_TCLTK is not defined.
- Added ability to exclude functions, tasks and named begin/end blocks with the -e score command
- Added ability to exclude all continuous assignments from coverage consideration with -ec score command
- Added ability to exclude all always blocks from coverage consideration with -ea score command
- Added ability to exclude all initial blocks from coverage consideration with -ei score command
- Fixed problem with race condition checker statement iterator to eliminate infinite looping.
- Also fixed expression assigment when static expressions are used in the LHS
- Fixed bug for signals that are on the LHS side of an assignment expression but are not being
assigned (bit selects) so that these are NOT considered for race conditions.
- Added simulation performance statistical information to end of score command when the -S option is
specified to the score command (this will probably only be useful for Covered developers but may
be interesting/useful for users later on).
- Fixing bug in expression_assign function -- removed recursive assignment when the LHS expression
is a signal, single-bit, multi-bit or static value (only recurse when the LHS is a CONCAT or
LIST).
- Fixing bug in report help information when Tcl/Tk is not available
- Lots of improvements to simulator to increase performance (this will be quite noticeable!)
- Documentation updates
- Regression suite enhancements (lots of new diagnostics added for testing new Verilog constructs as well
as testing bug fixes).
- Added cleanup function at exit which now automatically removes the temporary files that Covered creates
from the pre-processing step even when something goes drastically wrong while this file is opened.
Note: The format of the generated CDD files has changed quite a bit in format so you will not be able
to merge CDD files generated from older versions of Covered with CDD files generated from newer versions
of Covered (Covered will display an error message to the user stating this reason). As always, please
e-mail any bugs/problems found with this new release!
* 2/8/2005
Development release covered-20050208 made. This release primarily contains support for detecting
and handling race conditions with the DUT. Added flags to the score command control the behavior
of Covered when these race conditions are detected. Additionally, the race condition information
is saved to the CDD file for reporting purposes in both the text reports as well as the GUI. This
feature is not only useful to logic designers but also sets up Covered to provide better coverage
results going forward as well as allows Covered to gain coverage for some constructs that are
currently not supported. A few other bugs are fixed in this release as well as documentation
updates for the race condition usage. The following is a description of what has changed in this
release:
- Added support for detecting/handling race conditions in DUT
- Added ability to report race conditions to report command
- Fixing bug in file search algorithm. When a file was specified with a -v option after it
had already been included, an error was being reported and parsing stopped. In this case, it
now just ignores the duplicate include.
- Fixed preprocessor to ignore protected areas of code.
- Fixed library extension command-line parser.
- Changed was data is stored on a bit-basis for certain data types to use unions. Eases coding
and improves performance of score command just a bit.
- Added support for Verilog strings as static values. Strings can also be used in FSM value assignment
from command-line or from inline attribute.
- Ran -Wall compiler flag to clean up code.
- Added race condition run to regression
- Updated man page, User Guide and GUI documentation for changes
- Fixing bug in GUI where deselecting/selecting Covered, Uncovered or Race Condition in combinational
logic window would redisplay the file incorrectly.
- Added code to display help information in information bar of GUI main window when cursor is
over missed toggle and/or combinational logic coverage
- Added code to display reason for race condition when cursor is over lines that were discarded from
coverage consideration.
* 12/10/2004
Development release covered-20041210 made. This release contains summary and detailed coverage
reporting windows for toggle and combinational logic to the GUI. Lots of bug fixes, updates
and enhancements to the UI. The scoring phase was optimized a bit to improve run-time.
Additionally, help manual has been started for the current state of the GUI. The following
is a description of the changes found in this release over the last.
- Fixing case where user hits cancel button in the open CDD window and application exits.
- Added module/instance highlighting in listbox for uncovered modules/instances.
- Adding informational bar at the bottom of the main window for providing state-sensitive
help/state information.
- Added ability to make module/instance listbox resizable.
- Fixed configure files for Tcl/TK referencing.
- Fixed bug in getting the line summary total for the GUI.
- Fixed problem where source viewer would lose its place when switching between different
coverage metrics, changing colors and/or specifying different uncovered/covered options.
- Added 'Open Related CDD' and 'Merge related CDD' options to File menu to allow user to see
different CDD files generated from the same design and to merge CDD information from the
same design.
- Added verbose toggle coverage information window, allowing the user to see verbose information
for a signal by left-clicking on the signal in the source viewer.
- Added verbose combinational coverage information window, allowing the user to see verbose
information for an expression by left-clicking on the expression in the source viewer.
- Modified error reporting for GUI to display this information to an interactive window (instead
of the the shell).
- Added code to improve efficiency during scoring phase. The improvement is fairly minor at this
stage, but there is more to come with these changes.
- Added start of help manual documentation for GUI.
Lots of features, bug fixes, optimizations, documentation enhancements and build improvements in
this release. Please report any problems, and, as always, enjoy!
* 03/21/2004
Release covered-20040321 made. This release contains lots of bug fixes and also contains the
initial version of the Covered report viewing GUI (line coverage only). The following is a
description of the changes made since the last development release.
- Ran C linting tool on all Covered source code and updated code based on linting errors/
warnings.
- Modified debug output to show file and line number of code that called the outputting
function (easier to debug problems and useful in error regression testing).
- Started initial error testing in regressions.
- Several bug fixes made to remove segmentation faults and assertion errors in the new
report generation functions.
- Initial version of Covered report viewing GUI added. This version displays line coverage
only at the moment.
- Fixed bug in score command for statement removal (was resulting in memory errors that led
to segmentation faults).
- Fixed bug in report command that output bad verbose information when -c option was used.
- Added new diagnostics to regression testsuite to reproduce situations where original
segmentation faults were found to occur.
- Development documentation updates. No user documentation updates are released at this
time (other than information provided using the -h global option to Covered).
Have fun!
* 02/11/2004
Release covered-20040210 made. A lot of work has gone into this release to make the report
output more readable and concise. Several bug fixes have been made as well. A GUI is on
the way for report viewing that will be available in alpha version in the next development
release. Below are some of the highlights of this release.
- Added GUI interfacing functions in preparation of upcoming GUI report viewing utility.
- Added more information about expressions to line and combinational logic coverage verbose
information. Rather than just outputting the RHS of the expression, the LHS and assignment
operator (blocking or non-blocking) or IF statement are output to give the user a better
context of the missed logic.
- Fixed bug in param.c where parameters found in the RHS of expressions that were part of
statements being removed were not being properly removed.
- Fixed bug in sim.c where expressions in tree above conditional operator were not being
evaluated if conditional expression was not at the top of tree.
- Changed output of logic in combinational logic verbose coverage reporting to (by default)
use the same format (in terms of endline characters) as the logic was found in the source
code.
- Added '-w [<line_width>]' option to report command that causes combinational logic to be
output to report as much logic as will fit in the value of <line_width> in the report. A
default value of line width is specified internally in Covered to be 105 characters;
however, the user may make this value larger or smaller to suit. This value reverses the
effect of the above bulletin. Added this option to Covered's regression suite to test.
- Completely modified output format of missing combinational logic coverage. Removed a lot
of coverage information that was extraneous. When three or more subexpressions are ANDed,
ORed, logical ANDed, or logical ORed, coverage information is output in a special way to
increase readability/understandability for this coverage.
- Added "GENERAL INFORMATION" section to all reports which specifies general information
about this report (this eliminates a lot of redundant information in the report to improve
readability).
- Added the name of the CDD file from which a report has been generated from in the
GENERAL INFORMATION section of the report.
- When a CDD file is created due to merging CDD files, the names of the original CDD files
are now stored in the merged CDD file. This information is output in the GENERAL
INFORMATION section of the report (created from this merged CDD file) to indicate to the
user this information.
- If a CDD file is created due to merging CDD files and the leading hierarchies in each of
those CDD files are different, a bullet in the GENERAL INFORMATION specifies this and
reminds the user that the leading hierarchy information will not be output in the rest of
the report (instead the string "<NA>" replaces the leading hierarchy information). This
will help to eliminate confusion when viewing the reports and fixes an outstanding bug
in Covered.
- Added starting and ending line information to module structure for GUI purposes.
- Removed scope information in CDD file for expressions, signals and statements. This
information was not used, caused CDD files to become excessive in size and mildly speeds
up reading in CDD files.
- Fixed bugs in combinational logic report section where summary coverage numbers and verbose
coverage numbers did not agree.
- Removed 'c' directory in 'diags' directory and cleaned up Makefile to run regressions.
- Masked off the value of the SET bit in expressions output to CDD files. This information
is not needed and sometimes caused regression failures due to CDD file mismatches on
different platforms or using different simulators.
- Modified regression Makefile to specify the 'vvp' command prior to the compiled VVP
executable when running Icarus Verilog regressions (due to recent change to IV).
- Changed instance-based reports to not merge child instance coverage information into parent
instance coverage information. This is not done in module-based reports, makes reading
this information confusing and doesn't provide us any extra information.
- Fixed bug where modules were being reported in verbose reports when coverage numbers were
100% covered.
- Changed toggle coverage report output to output toggle information in hexidecimal format
versus binary format. This keeps the toggle coverage information more succinct/readable.
Added underlines between every 4th hexidecimal value to help user's to discern the bit
position of a toggle bit.
- Changed the format of the report entirely to enhance readability (many changes here that
the user will immediately see).
- Updated user documentation for new changes and added new section called "Reading the
Report" which will walk the user through several reports and how to interpret the report
information. This section is still in progress at this time.
- Updates to development documentation.
- Lots of new diagnostics added to regression suite. We now have over 200 diagnostics in this
regression.
Special note: Please note that the CDD file format for this release has changed from previous
CDD files and is therefore incompatible with older versions. If you try to read a CDD file
generated from an older version of Covered with the newer version, Covered will tell you that
this cannot be done due to incompatible CDD versions.
* 11/16/2003
Release covered-20031116 made. This development release contains a new way to specify FSMs
within the design by using inline Verilog-2001 attribute syntax. There are also a lot of
bug fixes contained in this release as well as the usual user and development documentation
enhancements. See the list below for more details on the changes made for this release.
- Added better VCD parsing capability to allow bit selects to be "attached" to the signal
names in the VCD variable definition section. The newer versions of Icarus Verilog now
output this format style.
- Added ability to specify FSM location and transition information using Verilog-2001
attributes. Added many diagnostics to regress suite to verify this capability.
- Fixed bug found in stable release that caused an incorrect calculation of unary operations
performed on single-bit values. Fixes bug 835366.
- Fixed bug found in using constant values in the right-hand side of repetitive concatenation
operators. Fixes bug 832730.
- Fixed bugs in reporting of FSM coverage information in the report command.
- Fixed bug in FSM variable binding stage that caused incorrect coverage numbers to be reported
for FSM coverage.
- Fixed bug in handling variables that are too long (more than the allowed 1024 bits). Removes
memory corruption problems when this occurs. Displays warning to user that it has found
a variable that it cannot handle and gracefully disregards any logic that uses these variables.
- Updated user documentation to include new chapter on inline attributes that Covered can
now handle.
- Updated development documentation for new functions added in this release.
* 10/19/2003
Release covered-20031019 made. Lots of modifications to existing structures and supporting
code to increase scoring speed. In my testbenches, I am seeing about a 3-4x improvement
in speed. Additionally, code enhancement for allowing bit selects and signal concatenations
in command-line FSM variable descriptions are now allowed. User documentation has been
updated for these changes. Some bug fixes are also included in this release. The
following list shows the changes from last development release.
- Added ability to parse more complex state "variables". This includes the ability
to specify single and multi-bit signals and the ability to concatenate more than
one signal (or signal bit select) to make a state variable. Please see user
documentation for more information on this.
- Minor tweaks to report format for displaying filenames (only basename of filename
is output instead of the entire path).
- Fixing bug in VCD parser to allow bit select parsing of a variable when the
variable name and bit-select information are not separated by spaces (this is something
that newer versions of Icarus Verilog now does in its VCD files).
- Changed structure for vectors from ints to chars. Each vector element stores information
for one 4-state bit value and its coverage information (instead of storing 4 4-state
variables and coverage information). This reduces memory needed and increases calculation
speed on vectors.
- Fixing bug in signal_from_string function.
- Fixing bug in arc.c related to non-zero LSBs of signals.
- Added new parameter to info line in CDD file that specifies the format of the CDD file.
This is used by Covered to keep CDD files with different formats from being merged, read,
etc.
- Removed LSB information from vector and storing this information in the signal
structure. Reduces memory required, enhances speed, and fixes existing bugs with bit
selects.
- Added more diagnostics to regression suite to test new functionality.
- Updated user documentation for new changes.
* 09/25/2003
Release covered-20030925 made. This release contains the first working FSM code
coverage portion in Covered. There is a lot more to work on in the FSM code coverage
area in the way of automatic FSM extraction and state transition specification, but
this version is able to extract FSM coverage information for an FSM that is located
by the user. Please see user's manual for this release for more details on specifying
FSM location. Summary and verbose reporting are available for FSM coverage at this
point. Additionally, the data format for FSM coverage information in the CDD file
has been finalized. FSM coverage merging is also supported in this release. User and
development documentation has been updated. Please give this development version a
go to get any bugs out of the FSM code coverage engine.
In addition to the FSM coverage support, a bug was fixed in the vector_to_int()
function when converting a vector whose LSB is a non-zero value.
Here is what is on the horizon for FSM coverage that you should expect to see in the
coming development releases.
- Ability for user to specify the location of an FSM using $attribute function.
- Ability for user to specify all possible state transitions for a given FSM on the
command-line and using inline $attribute functions.
- Automatic FSM extraction including locating an FSM and extracting all possible
state transitions.
* 08/20/2003 - Stable Release 0.2.1
Some bugs were found in the covered-0.2 release that needed to be fixed to consider
Covered to be completely stable. This release (covered-0.2.1) contains these fixes
which are outlined below. Please get a hold of this stable release if you have already
downloaded covered-0.2.
- Fixing bug with the initialization of the new symtable structure. Only 255 of the
256 children of each node were being initialized correctly. Fixes a segfault problem with
the symtable_dealloc routine.
- Fixed memory leak problem with file list in parser. This was a long outstanding problem
that has now been understood and fixed.
- Added fclose() after the VCD parsing was complete.
- Fixed a memory problem with the symtable structure that caused other data structure
values to be corrupted.
- Fixed assertion error problem with VCD symbol aliasing.
* 08/16/2003
Stable release covered-0.2 finally made! This release will be the springboard
for adding FSM coverage code, code optimizations as well as a few new features
that should make the score command run much faster. Some important bug fixes
were made in this release and code optimizations have been added to the score
command. If you are getting coverage for a larger design, you should definitely
notice the speed increase. In one of my designs, the speedup was a facter of
a bit more than 3x. The following are the list of changes made for this release.
- Added -ts option to score command to allow the user to see where in the
simulation process the score command is currently at. Please see user
documentation for more details on this new option.
- Fixed bug with multiple wait event statements within same always block.
This means that the CDD files created with the last version of Covered
will be incompatible with the new CDD files.
- Fixed bug with posedge, negedge and anyedge expressions when more than
one of these is found in the same always block.
- Fixed bug in vector comparison function. Vectors will now compare to a value
of true if the values of two vectors (whose bit size is different) are equal
up to the smallest MSB of the two vectors. Before, if two vectors were not
of equal size, a compare would always evaluate to FALSE.
- Removed unnecessary global variables.
- Removed generated development documentation from release and opted to
generate these with a user 'make' in the doc directory (makes release size
smaller and is unnecessary for most users anyways).
- Development documentation updated.
- User documentation and man file updated.
* 08/06/2003
Release covered-0.2pre3 made. It has been quite a while since a release has been made
which has been due to a particularly tricky bug that was found with non-blocking
assignments. This bug generated bad coverage information (this is considered very bad!)
This release contains bug fixes and development documentation updates. If no more problems
are found with this release, I will get the 0.2 release made very soon. The following
is a list of the changes for this release.
- Fixes to line.c and toggle.c to provide better cross-platform support.
- Lots of updates to the development documentation.
- Fixed bug with properly handling hierarchical references in expressions.
- Fixing bug with single-bit parameter handling (caused a diagnostic miscompare
between Linux and Irix OS's).
- Fixed non-blocking assignment bug. This bug affected the order of execution in
Covered's simulator which resulted in bad coverage information being generated.
- Fixed bugs in divide, mod, left shift, right shift and some other expression types
to avoid converting variables that have unknown values to integers (which results
in Covered errors at run-time).
The list of changes is short, but the changes made are very necessary to getting reliable
coverage numbers from Covered. Please get a copy of this version and test it out so that
we can get the stable 0.2 release made ASAP.
* 02/18/2003
Release covered-0.2pre2 made. Bug fixes and enhancements for allowing more Verilog
code to be parsed without spewing parsing errors. The list of open bugs is empty at
the moment. I will be working on enhancing the user documents and development
documents in preparation for the stable release. The stable release will be made
next unless there are new bugs found for which the bug fixes convince me that additional
testing is necessary. The following is a list of the changes for this release.
- Fixed bug with copying instance trees for instances of modules that were previously
parsed and built into the main instance tree.
- Fixing bug in file finder so that only missing modules are displayed after the
parsing phase is completed.
- Updated output of filenames as they are parsed to give more consistent look.
- Fixing bug with leftover tmp* file when missing module error is reported.
- Adding parsing support for pullup, pulldown and gate types though these are not
supported for coverage at the current time (probably will be supported after stable
release).
- Adding parsing support for real numbers in statement delays.
- Fixing case where statement is found to be unsupported in middle of statement tree.
The entire statement tree is removed from consideration for simulation.
- Added preliminary support for parsing attributes though the parsing support is not
complete at this time.
- Fixing bug with line ordering where case statement lines were not being output
to reports.
- Fixing bug with statement deallocation for NULL statements within statement trees.
- Updates to parser for new bison version 1.875
- Added support for named blocks
- Fixing bug with handling of preprocessor directives with leading whitespace.
- Fixes/optimizations to db_add_statement function which avoids stack overflow errors.
- Added check in regard to -i option to score command. Bad -i values would cause no
coverage information to be generated but would not tell user explicitly. Error
message now provided with -i option is not specified but is needed and/or -i option
is incorrect.
- Lots of parser updates to be able to parse UDPs, escaped identifiers, specify blocks,
and some other various Verilog code that was causing parse errors or assertion errors.
- Fixed proper handling of the event type.
- Fixed bug with merging constant/parameter vector values which caused assertion error
in report command when reporting on a merged file.
- Fixed user error message for merge command when CDD files are unable to be read.
- Added new type to CDD for general CDD file information. This allows CDD files from
different testbenches with the same DUT instantiated to be properly merged.
- Fixed problem with generating report from CDD file that has not been scored. Covered
detects that the CDD file has not been scored and outputs an error message to the user
not allowing them to generate these reports.
- Added support for reading bit selects from VCD files (this information was previously
ignored). This was necessary as other simulators bit blast module ports in VCD files.
- Updated look of instance reports to display full hierarchy of an instance instead of
the instance name and the instance name of the parent module. Much easier to locate
the instance in the design now.
- Fixed bug with using -D/-Q option with merge command.
- Added merge regression testing capability to regression suite.
- Updated build environment for RedHat 8.0 requirements.
- Updates to regression suite
- Development documentation updates.
The way that Covered looks and feels for 0.2 stable release is set in stone now. Please
make sure that you test this version as much as possible to get any leftover bugs out of
the code. I only plan on updating documentation, adding code comments, and fixing bugs.
If any bugs are sent in, a 0.2pre3 release will be created, otherwise, I will make
the 0.2 stable release available.
I've got some exciting things in Covered's future in plan after 0.2 stable release,
including FSM support, new text report look, code optimizations, support to be fully
Verilog-2001 compliant, a parallel scoring algorithm, and a new GTK+ interface.
Happy testing!
* 01/05/2003
Happy New Year! Release covered-0.2pre1_20030105 made. This release is primarily a
bug fix release; however, many of the bugs required larger changes than would be
expected before a stable release. The most significant change being to the lexer which
is now split into a preprocessor and a normal lexer (before these two functions were
combined into one). As such, this is the first prelease with a second release most
likely expected before stable release. The following is a list of changes included in
this release.
- Preprocessor split out from lexer to allow proper handling of defined values within
code.
- Added -p option to score command to allow user override of preprocessor intermediate
output file.
- Fixed bug where report output was not squelched when -Q global option specified on
report command line.
- Modified regression suite to verify CDD file generation (was being performed before),
module report generation (new) and instance report generation (new) to make sure that
report output was consistent.
- Fixed bug where integer, time, real, realtime and memory data types used in expressions
where considered to be implicitly defined and given 1-bit values. When these types
are seen in expressions now, they are ignored by Covered (caused nasty segfault).
- Fixed bug when a parameterized module is instantiated more than once in a design
(sent error message to user when this occurred).
- Fixed bug where a parsed module that was required but not at the head of the module
list was not being found by the parser.
- Added internal assertions and code to verify that we never try to overrun arrays
in the VCD parsing/running stage (caused nasty segmentation fault).
- Reorganized code for symtable symbol lookup and value assignment.
- Fixing bug where a parameterized module that was instantiated in a design more than
once was not getting the correct parameter value(s).
- Fixed module search algorithm to reparse a Verilog file that contains a module
that was previously ignored (not needed at the time) but is later found to be
needed.
- Created tree.c and tree.h to handle new module search algorithm and to replace
preprocessor define tree structure.
- Updated development documentation.
- Updates to user manual and manpage for new -p option, notes from this release
and a new section that starts to describe what logic is analyzed by Covered and
which code is not analyzed.
I've got some fairly large designs being run with this version of Covered and the regression
suite has grown to over 130 diagnostics with more on the way. Keep the bug reports coming!
* 12/14/2002
Release covered-20021214 made. This release is a bug fix release. See list below
for details. Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up. Please let me know if there are any other bugs that
need to be addressed before first stable release. Development documentation updated
to match changes in files. Regression suite has been updated quite a bit from last
time. There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).
- Segmentation fault fixes in report command
- Parser can now handle all net types (not just wire). Diagnostics added to regression
suite to verify their proper handling.
- Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
Diagnostics added to verify proper handling.
- Added human-understandable error messages in parser to help identify file and
line number along with a quasi-helpful error message description.
- When parser error is found, Covered exits after parsing phase without continuing
to write CDD file.
- Fixed bug where a multi-bit select expression existed in a module that was
instantiated more than once. Assertion error fired in this case.
- Updated regression suite for VCS testing.
- Fixed bug where parameters were used in modules that were instantiated more than
once.
- Fixed bug that dealt with parameters (see param6.1.v for test case).
- Fixed bug where a delay statement was the last statement in a statement block used
by Covered. Added diagnostics to verify correct behavior.
- Fixed infinite loop problem with db_add_statement function.
- Fixed infinite loop problem with statement_set_stop function.
- Fixed bug with parsing order. When an instance is found for a module that has
already been parsed, the instance was incorrectly being handled. Bug replicated
with instance6.v diagnostic.
- Fixed output of edge-triggered events to add @(...) around the expression (they
were easily confused with other code that could exist on the same line).
- Fixed bug in parser to not allow module to be parsed more than once.
- Fixed bug that lead to an assertion error (see instance6.1.v for test case).
- Fixing bug with calculating list and concatenation lengths when MBIT_SEL
expressions were included.
- Changed Covered's handling of -y directories. Before, all files in these directories
were fed into the parser to look for missing modules. Now, when a module is needed,
the module name is used to find the matching filename in the -y list (basically,
the -y option works like the -y option in Icarus Verilog and VCS). This fix really
streamlined the parsing phase and fixed several bugs.
- Memory declarations are now properly ignored (produced segmentation fault previously).
- Fixed report command to display all lines and expressions in order according to
their line number (the problem is REALLY fixed now).
- Removed hierarchical references from being scored.
All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read. Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some
things to work on for next release already.
* 11/27/2002
Release covered-20021127 made. This release contains mostly bug fixes to get closer
to first stable release. In addition, it should be noted that bug fixes to allow
Covered to work on 64-bit architectures have been added. The various bug fixes
have been listed below. User documentation, development documentation and regress
suite has been added to and enhanced.
- Reformatted parser.y code to make it more readable.
- Fixed bug in parser.y that existed in 20021026 which caused the bison parser
to either spew an error or warning
- Fixed bug in expression resizer that caused a segmentation fault for expressions
with NULL values in right side child expressions
- Fixed CVS automatic log commenting. This was causing /* to show up within
the Log comments. Resulted in the C compiler spewing warning messages.
- Fixed code that handles Verilog constructs that are not supported by Covered.
These caused segmentation faults previously. Any code not handled by Covered
should be ignored and cause the statement block to not be examined that contains
the ignored code.
- Fixed expression CDD file reader to read short numbers correctly.
- Fixed compatibility problems between cc and gcc compilers.
- Fixed problem that resulted in bus errors from the parser.
- Removing compiler warnings from source and header files. Code should now compile
clean when the -Wall option is provided to the compiler.
- Fixed problem where EXPAND expressions were failing when the multiplier of the
expander was an expression itself.
- Fixed problem with combinational logic output in the report command.
- Fixed bug when parameters are used in expression resizing.
- Verified that `ifdef cases work appropriately when parts of the `ifdef/`else/`endif
are commented out (bug found in Icarus Verilog)
- Added start of FAQ to user manual.
- Fixed bug in report command for underlining parameters in the reports.
- Fixed bugs with multi-bit and single-bit handling.
- Fixed bug with combinational logic being output when it is unmeasurable.
- Fixed bug in report command when an expression can be counted more than once. All
expressions are now only able to be counted and displayed once (removal of redundant
information).
- Fixed static expression calculation to yield proper coverage results for expressions
containing constant values.
- Verified -T option works correctly for min, typ, and max values.
- Changed delay specifier to only report a warning if min/typ/max is not specified and
we have parsed a delay with these specifiers. Still default to typ.
Keep the bug reports coming. I really want to get to first stable release as I have figured
out how to handle FSMs and want to start working on a GUI front-end for the report command.
* 10/26/2002
Release covered-20021026 finally made. This release is an enormous step toward
getting to first stable release. Added support for parameters which should be
complete for stable release. Supports all Verilog-1995 standard parameter code.
This caused some parts of the code to be completely redesigned and in the process
enhanced the efficiency of the score command. Additional enhancements and bug fixes
are so numerous that I will list them below:
- Fixed bug in VCD for reading $var definitions containing optional bit selects
- Fixed bug with calculating initial values of signals for all simulators
- Fixed bug with coverage results for static values.
- Modified regression to run with Icarus Verilog or VCS.
- Full support parameters as specified for Verilog-1995 (Verilog-2000 will be supported
in the future) -- simple bullet in list but a lot of work involved here.
- Fixing bug with concatenations specified on the left-hand-side of equations
- Fixed several other bugs in handling concatenations.
- Added lots of new diagnostics to regression suite to test parameters and other
Verilog components which were found to be buggy.
- Fixed bugs with single and mult-bit signal selects. Multi-bit select bugs were
causing internal assertion errors to fire.
- Expressions changed to be more efficient with memory consumption.
- Added ability to parse real types in VCD dumpfiles (though real numbers are not
supported internally) -- VCD dumpfile parsing should be complete now.
- Fixing -i option in score command to use full Verilog hierarchy rather than just
the instance name (this was the intended behavior).
- Added -T option to allow user to select min, typ, or max delay values in
min:typ:max delay statements.
- Fixed bug leading to segmentation fault in report command when outputting verbose
information for large expression trees.
- Added initial fix for ordering line and combinational logic outputs in verbose
reports (they were backwards before).
- Updates to development documentation, user manual, and man page for new features
and redescribed a few things in user manual for clarification purposes.
Overall, this is a MAJOR release. Please give this one a try and submit bug reports.
I only have a few more small features to add before first stable release so I want to
really work the problems out of this release. All Verilog code that Covered will
pay attention to in a design for the Verilog-1995 standard is now in place. A lot of
work went into this release -- thus the delay in getting the release out.
* 9/14/2002
Release covered-20020914 made. This release is mostly a feature release with a few
bug fixes in place. Code has been added and development documentation started to
handle parameters. To make Covered as efficient as possible in the score command,
certain unnecessary steps were removed; however, this makes supporting parameters
more complicated to code. I am narrowing in on the implementation but as of yet
parameter support is not included in this release. The next release should provide
support for parameters. I did make some progress on checking off a few of the things
on the TODO list before first stable release. I have added the initial version of
combinational logic depth control. When the -v option was present, all subexpressions
found to be not fully covered where output for combinational logic. This type of
output, though very useful, was somewhat too verbose to gain an understanding of
initial coverage information. To remedy the situation, I have removed the -v option
and added the -d (detail control) option which may take the following parameters:
s, summary output only; d, detail output (intermediate verbose output); and v, verbose
output (same as the old -v option). The information contained in detailed output is
similar to most commercial coverage tools that I have used. The -d v option will
provide that "over the top" information as to exactly what subexpressions where not
fully covered. Additionally, bug fixes were made to the -c option to the report command,
and MULTIPLY, DIVIDE and MOD expressions should now be output in detailed and verbose
reports. Fixed bug with initial value of signals that was causing Covered to report
incorrect coverage results for signals that were not initialized and not toggled during
simulation. Updated regression test suite for all changes mentioned above and updated
user, manpage and development documentation.
* 8/22/2002
Release covered-20020822 finally made. Took some time off away from the project to get
some other chores done and get refreshed. This release contains mostly bug fixes that I
have found while testing the tool on some "real" logic. The CDD database merging (used
in the merge and report commands) was rewritten for optimization purposes and to remove
a hard-to-pin-down segmentation fault. As a result, merging CDD files and generating
reports should be a bit faster and the bizarre bug should be eliminated. Fixed some
bugs in Verilog parser to generate user error/warning messages instead of core dumping.
Also added -c option to report command that allows the user (and maintainer) to generate
a report that shows what code is covered (instead of the default behavior to show what is
uncovered). This is useful for debugging and understanding exactly what the tool is
capable of measuring. Removed Bison generated VCD parser and replaced it with an optimized,
hand-written VCD parser. This should make reading in the VCD file much faster and should
totally eliminate any problems in reading in these files. Added manpage as an additional
documentation source and updated Makefiles to install this manpage. Updated user
documentation and development documentation.
* 7/21/2002
Release covered-20020721 made. Lots of bug fixes and feature enhancements. Fixed output
to a more understandable format when modules cannot be found during parsing. Added support
for the -e option which allows the user to omit modules from coverage. Fixed single and
multi-bit selectors. These should work properly now, selecting the correct values from
vectors. Added -D option to allow the user define values at the command-line. Fixed
problems associated with the `ifdef/`ifndef directives. Fixed problem with module trees
that were 3 or more modules deep. Created TODO list for items that I want to complete
before 0.1 stable release. This will give users/developers an insight to the short-term
goals of the project. All items in TODO list preceded by an X have also been worked on
in this release. Improved performance of signal/expression binding. Support has been
added to allow implicit wire declarations. Added ability to parse the design and score
the dumpfile in two calls to the score command. This could aid performance later as a
design would only need to be parsed once. More diagnostics have been added to the
Verilog test suite. Development and user documentation has been updated to bring them
up-to-date with current functionality.
* 7/15/2002
Release covered-20020715 made. Several bug fixes for problems found in previous release
and additional Verilog constructs are now supported. The `ifdef, `else, and `endif
directives are now supported. VCD scoping problems have been dealt with. It should be
possible now to get coverage results on an entire tree of Verilog instances. It should
also be possible to provide a dumpfile that contains more information than is necessary
for getting coverage. Some performance improvements have been made that will be noticeable
for larger designs. Fixed bugs for always statements that did not contain any coverage-able
code. Support is now in place for concatenation and replication in operations. The
binding phase has been revamped to provide better performance, easier maintenance and
less memory consumption. New diagnostics have been added to start testing new code support.
Full regression passes.
* 7/11/2002
Release covered-20020711 made. This release contains a lot of fixes to the score and report
commands. Proper support for `include and `define preprocessor now available. Fixes to the
-y, -I, and -f options to score command. These now seem to working correctly. Added -D and
-Q options to covered (for score, merge and report commands) for adjusting amount of output
to the screen. The -D option causes debug information to be spewed to standard output for
debugging tool problems (not recommended for standard usage). The -Q option will omit all
output to standard output (stderr is still displayed). By default, the minimal amount of output
is displayed to show tool progress. Added proper support for default case, casex and casez
statements. Fixed a lot of problems in the report command output, including reformatting the
toggle information to help make this more readable. Lots of bug fixes and support enhancements
make upgrading to this version worthwhile.
* 7/6/2002
Second release of Covered (covered-20020706) made. Proper support for case, casex and casez
now exists and has been tested to an extent. Fixed problem with reading VCD files appropriately.
Support for multi-bit anyedge (i.e., always @(b) ...) is now installed. Lots of other bugs
in the first release have been fixed. I have noticed a small performance degradation by changing
the VCD reader and am looking into it. All in all, this release fixes many bugs and enhances
support for case statements and always blocks.
* 7/3/2002
Finally release first unstable version of Covered in tarball format. This version should
be considered alpha at this point but may be considered ready for good testing. Please
read the release note that accompanies the pointer to the download for information on what
type of code is currently supported for testing purposes. Happy bug finding!
* 6/19/2002
Added beginnings of development on-line documentation. At the moment, this documentation
mostly lays out the ground-work for interested developers. Lots of details are missing at
the moment; though, the generated documentation contains a lot of source-code-specific
information. With initial documentation out of the way, for the most part, the first
release should be right around the corner.
* 5/1/2002
Added user on-line manual. The download still isn't available for use; however, it may be
interesting to see how the tool will be used. By the way, the download should be available
soon for first release. All of the features may not be present but it should be somewhat
usable.
* 4/12/2002
Created a home for the Covered utility on SourceForge.net. Currently, the HTML website is
only available for viewing. No downloads are yet available. There are a few features that
need to be added to the tool (and verification of those and other parts) before the source
files and tool become available for public use. Check out the ToDo page for items that are
on my todo list before making the tool available on-line!
* 11/27/2001
Started working on the Covered utility. After searching long and hard for a free, open
source code coverage utility and coming up empty, decided to start working on one. This
utility will be available on the gEDA website and database.
