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<html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968" /><title>Accessing the device</title><meta name="generator" content="DocBook XSL Stylesheets V1.75.2" /><link rel="home" href="index.html" title="Bus-Independent Device Accesses" /><link rel="up" href="ch03.html" title="Chapter 3. Memory Mapped IO" /><link rel="prev" href="ch03.html" title="Chapter 3. Memory Mapped IO" /><link rel="next" href="ch04.html" title="Chapter 4. Port Space Accesses" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Accessing the device</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ch03.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Memory Mapped IO</th><td width="20%" align="right"> <a accesskey="n" href="ch04.html">Next</a></td></tr></table><hr /></div><div class="sect1" title="Accessing the device"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="accessing_the_device"></a>Accessing the device</h2></div></div></div><p>
The part of the interface most used by drivers is reading and
writing memory-mapped registers on the device. Linux provides
interfaces to read and write 8-bit, 16-bit, 32-bit and 64-bit
quantities. Due to a historical accident, these are named byte,
word, long and quad accesses. Both read and write accesses are
supported; there is no prefetch support at this time.
</p><p>
The functions are named <code class="function">readb</code>,
<code class="function">readw</code>, <code class="function">readl</code>,
<code class="function">readq</code>, <code class="function">readb_relaxed</code>,
<code class="function">readw_relaxed</code>, <code class="function">readl_relaxed</code>,
<code class="function">readq_relaxed</code>, <code class="function">writeb</code>,
<code class="function">writew</code>, <code class="function">writel</code> and
<code class="function">writeq</code>.
</p><p>
Some devices (such as framebuffers) would like to use larger
transfers than 8 bytes at a time. For these devices, the
<code class="function">memcpy_toio</code>, <code class="function">memcpy_fromio</code>
and <code class="function">memset_io</code> functions are provided.
Do not use memset or memcpy on IO addresses; they
are not guaranteed to copy data in order.
</p><p>
The read and write functions are defined to be ordered. That is the
compiler is not permitted to reorder the I/O sequence. When the
ordering can be compiler optimised, you can use <code class="function">
__readb</code> and friends to indicate the relaxed ordering. Use
this with care.
</p><p>
While the basic functions are defined to be synchronous with respect
to each other and ordered with respect to each other the busses the
devices sit on may themselves have asynchronicity. In particular many
authors are burned by the fact that PCI bus writes are posted
asynchronously. A driver author must issue a read from the same
device to ensure that writes have occurred in the specific cases the
author cares. This kind of property cannot be hidden from driver
writers in the API. In some cases, the read used to flush the device
may be expected to fail (if the card is resetting, for example). In
that case, the read should be done from config space, which is
guaranteed to soft-fail if the card doesn't respond.
</p><p>
The following is an example of flushing a write to a device when
the driver would like to ensure the write's effects are visible prior
to continuing execution.
</p><pre class="programlisting">
static inline void
qla1280_disable_intrs(struct scsi_qla_host *ha)
{
struct device_reg *reg;
reg = ha->iobase;
/* disable risc and host interrupts */
WRT_REG_WORD(&reg->ictrl, 0);
/*
* The following read will ensure that the above write
* has been received by the device before we return from this
* function.
*/
RD_REG_WORD(&reg->ictrl);
ha->flags.ints_enabled = 0;
}
</pre><p>
In addition to write posting, on some large multiprocessing systems
(e.g. SGI Challenge, Origin and Altix machines) posted writes won't
be strongly ordered coming from different CPUs. Thus it's important
to properly protect parts of your driver that do memory-mapped writes
with locks and use the <code class="function">mmiowb</code> to make sure they
arrive in the order intended. Issuing a regular <code class="function">readX
</code> will also ensure write ordering, but should only be used
when the driver has to be sure that the write has actually arrived
at the device (not that it's simply ordered with respect to other
writes), since a full <code class="function">readX</code> is a relatively
expensive operation.
</p><p>
Generally, one should use <code class="function">mmiowb</code> prior to
releasing a spinlock that protects regions using <code class="function">writeb
</code> or similar functions that aren't surrounded by <code class="function">
readb</code> calls, which will ensure ordering and flushing. The
following pseudocode illustrates what might occur if write ordering
isn't guaranteed via <code class="function">mmiowb</code> or one of the
<code class="function">readX</code> functions.
</p><pre class="programlisting">
CPU A: spin_lock_irqsave(&dev_lock, flags)
CPU A: ...
CPU A: writel(newval, ring_ptr);
CPU A: spin_unlock_irqrestore(&dev_lock, flags)
...
CPU B: spin_lock_irqsave(&dev_lock, flags)
CPU B: writel(newval2, ring_ptr);
CPU B: ...
CPU B: spin_unlock_irqrestore(&dev_lock, flags)
</pre><p>
In the case above, newval2 could be written to ring_ptr before
newval. Fixing it is easy though:
</p><pre class="programlisting">
CPU A: spin_lock_irqsave(&dev_lock, flags)
CPU A: ...
CPU A: writel(newval, ring_ptr);
CPU A: mmiowb(); /* ensure no other writes beat us to the device */
CPU A: spin_unlock_irqrestore(&dev_lock, flags)
...
CPU B: spin_lock_irqsave(&dev_lock, flags)
CPU B: writel(newval2, ring_ptr);
CPU B: ...
CPU B: mmiowb();
CPU B: spin_unlock_irqrestore(&dev_lock, flags)
</pre><p>
See tg3.c for a real world example of how to use <code class="function">mmiowb
</code>
</p><p>
PCI ordering rules also guarantee that PIO read responses arrive
after any outstanding DMA writes from that bus, since for some devices
the result of a <code class="function">readb</code> call may signal to the
driver that a DMA transaction is complete. In many cases, however,
the driver may want to indicate that the next
<code class="function">readb</code> call has no relation to any previous DMA
writes performed by the device. The driver can use
<code class="function">readb_relaxed</code> for these cases, although only
some platforms will honor the relaxed semantics. Using the relaxed
read functions will provide significant performance benefits on
platforms that support it. The qla2xxx driver provides examples
of how to use <code class="function">readX_relaxed</code>. In many cases,
a majority of the driver's <code class="function">readX</code> calls can
safely be converted to <code class="function">readX_relaxed</code> calls, since
only a few will indicate or depend on DMA completion.
</p></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="ch03.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="ch03.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="ch04.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Chapter 3. Memory Mapped IO </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 4. Port Space Accesses</td></tr></table></div></body></html>
