From: Bhavna Sarathy <bnagendr@redhat.com> Date: Thu, 5 Aug 2010 18:03:21 -0400 Subject: [edac] amd64_edac: fix k8 chip select reporting Message-id: <20100805180900.6566.3010.sendpatchset@localhost.localdomain> Patchwork-id: 27416 O-Subject: [RHEL5.6 PATCH 2/10] amd64_edac - Fix k8 chip select reporting Bugzilla: 568576 RH-Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com> >From a6a209a579fe80411abc2872d07d228a8d4aaa74 Mon Sep 17 00:00:00 2001 From: Borislav Petkov <borislav.petkov@amd.com> Date: Sat, 31 Jul 2010 02:57:45 +0200 Subject: [PATCH] amd64_edac: fix K8 chip select reporting (Upstream commit 603adaf6b3e37450235f0ddb5986b961b3146a79) Fix the case when amd64_debug_display_dimm_sizes() reports only half the amount of DRAM on it because it doesn't account for when the single DCT operates in 128-bit mode and merges chip selects from different DIMMs. Reported-by: Johannes Hirte <johannes.hirte@fem.tu-ilmenau.de> LKML-Reference: <200912112202.48173.johannes.hirte@fem.tu-ilmenau.de> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 4b8c60c..3d4ec39 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1468,11 +1468,15 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, int ganged) { - int dimm, size0, size1; - u32 dbam; - u32 *dcsb; + int dimm, size0, size1, factor = 0; + u32 dbam; + u32 *dcsb; if (boot_cpu_data.x86 == 0xf) { + + if (pvt->dclr0 & F10_WIDTH_128) + factor = 1; + /* K8 families < revF not supported yet */ if (pvt->ext_model < K8_REV_F) return; @@ -1500,9 +1504,9 @@ static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, debugf1(" CTRL-%d CS%d=%5dMB CS%d=%5dMB\n", ctrl, dimm * 2, - size0, + size0 << factor, dimm * 2 + 1, - size1); + size1 << factor); } }