From: John Feeney <jfeeney@redhat.com> Date: Fri, 18 Dec 2009 16:07:25 -0500 Subject: [net] update tg3 driver to version 3.100 Message-id: <4B2BA8BD.8090009@redhat.com> Patchwork-id: 22140 O-Subject: Re: [RHEL5.5 PATCH REPOST] Update tg3 to version 3.104 Bugzilla: 515312 bz515312 https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=515312 Update tg3 to version 3.100 Description of problem: The previously posted patch was found to cause memory corruption panics in Connectathon when running with the debug x86_64 kernel. Since the cause of these panics is yet to be determined, this repost of tg3.c reduces the number of versions updated (3.100 vs 3.104) and as a result, does not contain any patches that involve alloc and free which is where the panics occurred. So the enclosed patch updates tg3.c from version 3.96-1 (Dec 2008) to version 3.100 (Aug 25, 2009). The remainder of the originally posted set will be dealt with at a later time, after the problem has been solved. Solution: Port as many upstream tg3 patches as possible, given the current functionality of RHEL5 in general and tg3.c in particular. Upstream status: The following upstream patches are included: 1. Glendinning - Move flow control to mii.h e18ce3465477502108187c6c08b6423fb784a313 (12/16/08) 2. Glendinning - Refactor full duplex bc02ff95fe4ebd3e5ee7455c0aa6f76ebe39ebca (12/16/08) 3. Carlson - Remove unused cfgspc device members 69fc405318967c7913e5b55cf3906250a26b49d0 (12/22/08) 4. Carlson - tg3.h cleanups aa10f27d99410cff9145bf91b6efc884c7a4871c (12/22/08) 5. Carlson - version 3.97 d3d317092b58a6df1d31a4ca90cdb9d2bd4ebffa (12/10/08) 6. Kluin - limit reaches -1 d4675b52a933831d4901217564cba5a434ddd922 (2/13/09) 7. Carlson - Fix 5906 link problems a6435f3a53746a0eb687a9f636cf1941f35f935e (2/27/09) 8. Carlson - Drop non-VLAN rx pkts f7b493e02101bb5a0a69a91a8b4b7b002cd60eaf (2/27/09) 9. Carlson - update ethtool set_settings error checks 7e5856bd9644e2299adbf5d0a8916f9cc56f1f36 (2/27/09) 10. Carlson - redefine tg3_vlan_rx_register() 844b3eed8a9efffa4225c811b989c8ff41691a78 (2/27/09) 11. Carlson - Eliminate nvram routine forward declarations ffbcfed441b9ba74ce77f215eed6925f6a0b82a3 (2/27/09) 12. Carlson - invert nvram_read and nvram_read_swab e4f341103e4a2b35f56a0f89802f1b1448e8d04b (2/27/09) 13. Carlson - Correct NVRAM stream endian notations a9dc529dcd5c541c51cb2ba09bff99580361c576 (2/27/09) 14. Carlson - Eliminate tg3_nvram_read_swab() 6d348f2c1e0bb1cf7a494b51fc921095ead3f6ae (2/27/09) 15. Carlson - Refactor firmware version routines acd9c119cc663860fff4f1445ed0f87d82378d99 (2/27/09) 16. Carlson - Add legacy bootcode decoding ff3a7cb25217bddcefd20e72af08a65481db4096 (2/27/09) 17. Carlson - Add DASH firmware version reporting 7fd764455a13f4d9b37c9b908f07d0758f11d3c5 (2/27/09) 18. Carlson - Add version reporting for hardware selfboot a6f6cb1cf8ba54efdbbbf61b5b4345b0246da42f (2/27/09) 19. Carlson - 3.98 Feb 2009 0d2a5068aaa238eba971784585e44130db6d4759 (2/27/09) 20. Carlson - Fix 5906 link problems 9f8ac0b7b063be77f0de7a27fe5e6a0aa2cce58d (3/4/09) 21. Andrew - Fix misspelling of firmware 877d03105d04b2c13e241130277fa69c8d2564f0 (3/30/09) 22. Yang - dma_mapping: replace all DMA64BIT_MASK 6a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01 (4/7/09) 23. Yang - dma_mapping: replace all DMA40BIT_MASK 50cf156af7dc68a44409bef636585ef88ebbab34 (4/7/09) 24. Yang - dma_mapping: replace all DMA32BIT_MASK 284901a90a9e0b812ca3f5f852cbbfb60d10249d (4/7/09) 25. Bottomley - fix big endian MAC addr collection failure 0d489ffb76de0fe804cf06a9d4d11fa7342d74b9 (4/13/09) 26. Carlson - Fix SEEPROM accesses 62cedd11f63c99efd2962fb69763a09e2778f6e6 (4/20/09) 27. Carlson - Handle NVRAM absent cases df259d8cba7d7880dc04d34c7a6e0ce15fbc9644 (4/21/09) 28. Carlson - Prevent send BD corruption 33466d938f43ab65312466ba5472b9c6ee200cce (4/21/09) 29. Carlson - Allow 5761 WOL and LED fixes to 5761S 8d519ab2866c92f5d722085492a124f016f601aa (4/21/09) 30. Carlson - Limit CLKREQ fix to A[01] of 57780 asic rev 9cf74ebb634fe79587cf9a1d5ff971391dd12e1b (4/21/09) 31. Carlson - Restore LAA sooner in shutdown daba2a631d2b7831b6a021b36d61314a9153526e (4/21/09) 32. Carlson - Version 3.99 April 20, 2009 bb9e63e27117b469a151c61fb0045a8ec4cced5d (4/21/09) 33. Carlson - Fix 57780 asic rev PCIe link receiver errors 521e6b90dd3f0392062845d7ef13e6e41bb99d8a (8/26/09) 34. Carlson - Prevent tx BD corruption 255ca311b650caece3ec4f78b88ef298664d561f (8/26/09) 35. Carlson - Fix TSO test against wrong flags var 29ea095fb727ac48228ff2d1af484c27bf1dcbd4 (8/26/09) 36. Carlson - Add 57788, remove 57720 5e7ccf2003e6a9c35b5aa24953ba5009a1a8b653 (8/26/09) 37. Carlson - Create MII_TG3_FET namespace 535ef6e1124d445efbcc13b7126561dc544b0b64 (8/26/09) 38. Carlson - VERSION 3.100 Aug 25, 2009 f656f39801b00c3c2aa26cefbdee2775d6706d45 (8/26/09) Brew: Successfully built in Brew for all architectures (task_2158558). Testing: I ran Connectathon successfully 10 times on systems with tg3 with the debug kernel and 4 times with the x86_64 kernel. Acks would be appreciated. Signed-off-by: Jarod Wilson <jarod@redhat.com> diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 730178e..bcee26f 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -4,7 +4,7 @@ * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) * Copyright (C) 2004 Sun Microsystems Inc. - * Copyright (C) 2005-2007 Broadcom Corporation. + * Copyright (C) 2005-2009 Broadcom Corporation. * * Firmware is: * Derived from proprietary unpublished source code, @@ -63,14 +63,12 @@ #define TG3_VLAN_TAG_USED 0 #endif -#define TG3_TSO_SUPPORT 1 - #include "tg3.h" #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "3.96-1" -#define DRV_MODULE_RELDATE "November 21, 2008" +#define DRV_MODULE_VERSION "3.100" +#define DRV_MODULE_RELDATE "August 25, 2009" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -217,7 +215,7 @@ static struct pci_device_id tg3_pci_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)}, + {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, @@ -846,7 +844,7 @@ static int tg3_bmcr_reset(struct tg3 *tp) } udelay(10); } - if (limit <= 0) + if (limit < 0) return -EBUSY; return 0; @@ -1026,9 +1024,9 @@ static void tg3_link_report(struct tg3 *tp) printk(KERN_INFO PFX "%s: Flow control is %s for TX and %s for RX.\n", tp->dev->name, - (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ? + (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? "on" : "off", - (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ? + (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? "on" : "off"); tg3_ump_link_report(tp); } @@ -1038,11 +1036,11 @@ static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) { u16 miireg; - if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX)) + if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) miireg = ADVERTISE_PAUSE_CAP; - else if (flow_ctrl & TG3_FLOW_CTRL_TX) + else if (flow_ctrl & FLOW_CTRL_TX) miireg = ADVERTISE_PAUSE_ASYM; - else if (flow_ctrl & TG3_FLOW_CTRL_RX) + else if (flow_ctrl & FLOW_CTRL_RX) miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; else miireg = 0; @@ -1054,11 +1052,11 @@ static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) { u16 miireg; - if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX)) + if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) miireg = ADVERTISE_1000XPAUSE; - else if (flow_ctrl & TG3_FLOW_CTRL_TX) + else if (flow_ctrl & FLOW_CTRL_TX) miireg = ADVERTISE_1000XPSE_ASYM; - else if (flow_ctrl & TG3_FLOW_CTRL_RX) + else if (flow_ctrl & FLOW_CTRL_RX) miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; else miireg = 0; @@ -1066,28 +1064,6 @@ static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) return miireg; } -static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv) -{ - u8 cap = 0; - - if (lcladv & ADVERTISE_PAUSE_CAP) { - if (lcladv & ADVERTISE_PAUSE_ASYM) { - if (rmtadv & LPA_PAUSE_CAP) - cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX; - else if (rmtadv & LPA_PAUSE_ASYM) - cap = TG3_FLOW_CTRL_RX; - } else { - if (rmtadv & LPA_PAUSE_CAP) - cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX; - } - } else if (lcladv & ADVERTISE_PAUSE_ASYM) { - if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM)) - cap = TG3_FLOW_CTRL_TX; - } - - return cap; -} - static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) { u8 cap = 0; @@ -1095,16 +1071,16 @@ static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) if (lcladv & ADVERTISE_1000XPAUSE) { if (lcladv & ADVERTISE_1000XPSE_ASYM) { if (rmtadv & LPA_1000XPAUSE) - cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX; + cap = FLOW_CTRL_TX | FLOW_CTRL_RX; else if (rmtadv & LPA_1000XPAUSE_ASYM) - cap = TG3_FLOW_CTRL_RX; + cap = FLOW_CTRL_RX; } else { if (rmtadv & LPA_1000XPAUSE) - cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX; + cap = FLOW_CTRL_TX | FLOW_CTRL_RX; } } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) - cap = TG3_FLOW_CTRL_TX; + cap = FLOW_CTRL_TX; } return cap; @@ -1121,13 +1097,13 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); else - flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv); + flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); } else flowctrl = tp->link_config.flowctrl; tp->link_config.active_flowctrl = flowctrl; - if (flowctrl & TG3_FLOW_CTRL_RX) + if (flowctrl & FLOW_CTRL_RX) tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; else tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; @@ -1135,7 +1111,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) if (old_rx_mode != tp->rx_mode) tw32_f(MAC_RX_MODE, tp->rx_mode); - if (flowctrl & TG3_FLOW_CTRL_TX) + if (flowctrl & FLOW_CTRL_TX) tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; else tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; @@ -1154,7 +1130,8 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) { u32 reg; - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) + if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) return; reg = MII_TG3_MISC_SHDW_WREN | @@ -1189,17 +1166,19 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { u32 ephy; - if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) { - tg3_writephy(tp, MII_TG3_EPHY_TEST, - ephy | MII_TG3_EPHY_SHADOW_EN); - if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) { + if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { + u32 reg = MII_TG3_FET_SHDW_MISCCTRL; + + tg3_writephy(tp, MII_TG3_FET_TEST, + ephy | MII_TG3_FET_SHADOW_EN); + if (!tg3_readphy(tp, reg, &phy)) { if (enable) - phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX; + phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; else - phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX; - tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy); + phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; + tg3_writephy(tp, reg, phy); } - tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy); + tg3_writephy(tp, MII_TG3_FET_TEST, ephy); } } else { phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | @@ -1284,7 +1263,7 @@ static int tg3_wait_macro_done(struct tg3 *tp) break; } } - if (limit <= 0) + if (limit < 0) return -EBUSY; return 0; @@ -1593,7 +1572,7 @@ out: if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { /* adjust output voltage */ - tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12); + tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); } else { u32 brcmtest; if (!tg3_readphy(tp, MII_TG3_FET_TEST, &brcmtest) && @@ -1644,7 +1623,8 @@ static void tg3_frob_aux_power(struct tg3 *tp) GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); - } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) { + } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || + tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | @@ -1744,8 +1724,6 @@ static int tg3_setup_phy(struct tg3 *, int); static void tg3_write_sig_post_reset(struct tg3 *, int); static int tg3_halt_cpu(struct tg3 *, u32); -static int tg3_nvram_lock(struct tg3 *); -static void tg3_nvram_unlock(struct tg3 *); static void tg3_power_down_phy(struct tg3 *tp) { @@ -1798,6 +1776,200 @@ static void tg3_power_down_phy(struct tg3 *tp) tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); } +static int tg3_nvram_lock(struct tg3 *tp) +{ + if (tp->tg3_flags & TG3_FLAG_NVRAM) { + int i; + + if (tp->nvram_lock_cnt == 0) { + tw32(NVRAM_SWARB, SWARB_REQ_SET1); + for (i = 0; i < 8000; i++) { + if (tr32(NVRAM_SWARB) & SWARB_GNT1) + break; + udelay(20); + } + if (i == 8000) { + tw32(NVRAM_SWARB, SWARB_REQ_CLR1); + return -ENODEV; + } + } + tp->nvram_lock_cnt++; + } + return 0; +} + +/* tp->lock is held. */ +static void tg3_nvram_unlock(struct tg3 *tp) +{ + if (tp->tg3_flags & TG3_FLAG_NVRAM) { + if (tp->nvram_lock_cnt > 0) + tp->nvram_lock_cnt--; + if (tp->nvram_lock_cnt == 0) + tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); + } +} + +/* tp->lock is held. */ +static void tg3_enable_nvram_access(struct tg3 *tp) +{ + if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && + !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { + u32 nvaccess = tr32(NVRAM_ACCESS); + + tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); + } +} + +/* tp->lock is held. */ +static void tg3_disable_nvram_access(struct tg3 *tp) +{ + if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && + !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { + u32 nvaccess = tr32(NVRAM_ACCESS); + + tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); + } +} + +static int tg3_nvram_read_using_eeprom(struct tg3 *tp, + u32 offset, u32 *val) +{ + u32 tmp; + int i; + + if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) + return -EINVAL; + + tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | + EEPROM_ADDR_DEVID_MASK | + EEPROM_ADDR_READ); + tw32(GRC_EEPROM_ADDR, + tmp | + (0 << EEPROM_ADDR_DEVID_SHIFT) | + ((offset << EEPROM_ADDR_ADDR_SHIFT) & + EEPROM_ADDR_ADDR_MASK) | + EEPROM_ADDR_READ | EEPROM_ADDR_START); + + for (i = 0; i < 1000; i++) { + tmp = tr32(GRC_EEPROM_ADDR); + + if (tmp & EEPROM_ADDR_COMPLETE) + break; + msleep(1); + } + if (!(tmp & EEPROM_ADDR_COMPLETE)) + return -EBUSY; + + tmp = tr32(GRC_EEPROM_DATA); + + /* + * The data will always be opposite the native endian + * format. Perform a blind byteswap to compensate. + */ + *val = swab32(tmp); + + return 0; +} + +#define NVRAM_CMD_TIMEOUT 10000 + +static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) +{ + int i; + + tw32(NVRAM_CMD, nvram_cmd); + for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { + udelay(10); + if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { + udelay(10); + break; + } + } + + if (i == NVRAM_CMD_TIMEOUT) + return -EBUSY; + + return 0; +} + +static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) +{ + if ((tp->tg3_flags & TG3_FLAG_NVRAM) && + (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && + (tp->tg3_flags2 & TG3_FLG2_FLASH) && + !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && + (tp->nvram_jedecnum == JEDEC_ATMEL)) + + addr = ((addr / tp->nvram_pagesize) << + ATMEL_AT45DB0X1B_PAGE_POS) + + (addr % tp->nvram_pagesize); + + return addr; +} + +static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) +{ + if ((tp->tg3_flags & TG3_FLAG_NVRAM) && + (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && + (tp->tg3_flags2 & TG3_FLG2_FLASH) && + !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && + (tp->nvram_jedecnum == JEDEC_ATMEL)) + + addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * + tp->nvram_pagesize) + + (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); + + return addr; +} + +/* NOTE: Data read in from NVRAM is byteswapped according to + * the byteswapping settings for all other register accesses. + * tg3 devices are BE devices, so on a BE machine, the data + * returned will be exactly as it is seen in NVRAM. On a LE + * machine, the 32-bit value will be byteswapped. + */ +static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) +{ + int ret; + + if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) + return tg3_nvram_read_using_eeprom(tp, offset, val); + + offset = tg3_nvram_phys_addr(tp, offset); + + if (offset > NVRAM_ADDR_MSK) + return -EINVAL; + + ret = tg3_nvram_lock(tp); + if (ret) + return ret; + + tg3_enable_nvram_access(tp); + + tw32(NVRAM_ADDR, offset); + ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + if (ret == 0) + *val = tr32(NVRAM_RDDATA); + + tg3_disable_nvram_access(tp); + + tg3_nvram_unlock(tp); + + return ret; +} + +/* Ensures NVRAM data is in bytestream format. */ +static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) +{ + u32 v; + int res = tg3_nvram_read(tp, offset, &v); + if (!res) + *val = cpu_to_be32(v); + return res; +} + /* tp->lock is held. */ static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) { @@ -1923,8 +2095,6 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) } } - __tg3_set_mac_addr(tp, 0); - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { u32 val; @@ -2650,6 +2820,15 @@ relink: pci_write_config_word(tp->pdev, tp->pcie_cap + PCI_EXP_LNKCTL, newlnkctl); + } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) { + u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL); + if (tp->link_config.active_speed == SPEED_100 || + tp->link_config.active_speed == SPEED_10) + newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; + else + newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN; + if (newreg != oldreg) + tw32(TG3_PCIE_LNKCTL, newreg); } if (current_link_up != netif_carrier_ok(tp->dev)) { @@ -4023,6 +4202,13 @@ static int tg3_rx(struct tg3 *tp, int budget) skb->ip_summed = CHECKSUM_NONE; skb->protocol = eth_type_trans(skb, tp->dev); + + if (len > (tp->dev->mtu + ETH_HLEN) && + skb->protocol != htons(ETH_P_8021Q)) { + dev_kfree_skb(skb); + goto next_pkt; + } + #if TG3_VLAN_TAG_USED if (tp->vlgrp != NULL && desc->type_flags & RXD_FLAG_VLAN) { @@ -4455,7 +4641,7 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, { #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) - return (((u64) mapping + len) > DMA_40BIT_MASK); + return (((u64) mapping + len) > DMA_BIT_MASK(40)); return 0; #else return 0; @@ -5319,62 +5505,6 @@ static int tg3_abort_hw(struct tg3 *tp, int silent) return err; } -/* tp->lock is held. */ -static int tg3_nvram_lock(struct tg3 *tp) -{ - if (tp->tg3_flags & TG3_FLAG_NVRAM) { - int i; - - if (tp->nvram_lock_cnt == 0) { - tw32(NVRAM_SWARB, SWARB_REQ_SET1); - for (i = 0; i < 8000; i++) { - if (tr32(NVRAM_SWARB) & SWARB_GNT1) - break; - udelay(20); - } - if (i == 8000) { - tw32(NVRAM_SWARB, SWARB_REQ_CLR1); - return -ENODEV; - } - } - tp->nvram_lock_cnt++; - } - return 0; -} - -/* tp->lock is held. */ -static void tg3_nvram_unlock(struct tg3 *tp) -{ - if (tp->tg3_flags & TG3_FLAG_NVRAM) { - if (tp->nvram_lock_cnt > 0) - tp->nvram_lock_cnt--; - if (tp->nvram_lock_cnt == 0) - tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); - } -} - -/* tp->lock is held. */ -static void tg3_enable_nvram_access(struct tg3 *tp) -{ - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && - !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { - u32 nvaccess = tr32(NVRAM_ACCESS); - - tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); - } -} - -/* tp->lock is held. */ -static void tg3_disable_nvram_access(struct tg3 *tp) -{ - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && - !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { - u32 nvaccess = tr32(NVRAM_ACCESS); - - tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); - } -} - static void tg3_ape_send_event(struct tg3 *tp, u32 event) { int i; @@ -5700,6 +5830,11 @@ static int tg3_chip_reset(struct tg3 *tp) smp_mb(); synchronize_irq(tp->pdev->irq); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { + val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; + tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); + } + /* do the reset */ val = GRC_MISC_CFG_CORECLK_RESET; @@ -5903,6 +6038,8 @@ static int tg3_halt(struct tg3 *tp, int kind, int silent) tg3_abort_hw(tp, silent); err = tg3_chip_reset(tp); + __tg3_set_mac_addr(tp, 0); + tg3_write_sig_legacy(tp, kind); tg3_write_sig_post_reset(tp, kind); @@ -6915,6 +7052,27 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(TG3_CPMU_HST_ACC, val); } + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { + val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; + val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | + PCIE_PWR_MGMT_L1_THRESH_4MS; + tw32(PCIE_PWR_MGMT_THRESH, val); + + val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; + tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); + + tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); + } + + if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) { + val = tr32(TG3_PCIE_LNKCTL); + if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) + val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS; + else + val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS; + tw32(TG3_PCIE_LNKCTL, val); + } + /* This works around an issue with Athlon chipsets on * B3 tigon3 silicon. This bit has no effect on any * other revision. But do not set this on PCI Express @@ -7177,7 +7335,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) __tg3_set_mac_addr(tp, 0); /* MTU + ethernet header + FCS + optional VLAN tag */ - tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8); + tw32(MAC_RX_MTU_SIZE, + tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); /* The slot time is changed by tg3_setup_phy if we * run at gigabit with half duplex. @@ -7359,7 +7518,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { - if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) && + if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { /* nothing */ @@ -8693,17 +8852,16 @@ static int tg3_get_eeprom_len(struct net_device *dev) return tp->nvram_size; } -static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val); -static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val); -static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val); - static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) { struct tg3 *tp = netdev_priv(dev); int ret; u8 *pd; u32 i, offset, len, b_offset, b_count; - __le32 val; + __be32 val; + + if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) + return -EINVAL; if (tp->link_config.phy_is_low_power) return -EAGAIN; @@ -8722,7 +8880,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, /* i.e. offset=1 len=2 */ b_count = len; } - ret = tg3_nvram_read_le(tp, offset-b_offset, &val); + ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); if (ret) return ret; memcpy(data, ((char*)&val) + b_offset, b_count); @@ -8734,7 +8892,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, /* read bytes upto the last 4 byte boundary */ pd = &data[eeprom->len]; for (i = 0; i < (len - (len & 3)); i += 4) { - ret = tg3_nvram_read_le(tp, offset + i, &val); + ret = tg3_nvram_read_be32(tp, offset + i, &val); if (ret) { eeprom->len += i; return ret; @@ -8748,7 +8906,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, pd = &data[eeprom->len]; b_count = len & 3; b_offset = offset + len - b_count; - ret = tg3_nvram_read_le(tp, b_offset, &val); + ret = tg3_nvram_read_be32(tp, b_offset, &val); if (ret) return ret; memcpy(pd, &val, b_count); @@ -8765,12 +8923,13 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, int ret; u32 offset, len, b_offset, odd_len; u8 *buf; - __le32 start, end; + __be32 start, end; if (tp->link_config.phy_is_low_power) return -EAGAIN; - if (eeprom->magic != TG3_EEPROM_MAGIC) + if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || + eeprom->magic != TG3_EEPROM_MAGIC) return -EINVAL; offset = eeprom->offset; @@ -8778,7 +8937,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, if ((b_offset = (offset & 3))) { /* adjustments to start on required 4 byte boundary */ - ret = tg3_nvram_read_le(tp, offset-b_offset, &start); + ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); if (ret) return ret; len += b_offset; @@ -8792,7 +8951,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, /* adjustments to end on required 4 byte boundary */ odd_len = 1; len = (len + 3) & ~3; - ret = tg3_nvram_read_le(tp, offset+len-4, &end); + ret = tg3_nvram_read_be32(tp, offset+len-4, &end); if (ret) return ret; } @@ -8845,7 +9004,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) cmd->duplex = tp->link_config.active_duplex; } cmd->phy_address = PHY_ADDR; - cmd->transceiver = 0; + cmd->transceiver = XCVR_INTERNAL; cmd->autoneg = tp->link_config.autoneg; cmd->maxtxpkt = 0; cmd->maxrxpkt = 0; @@ -8856,26 +9015,58 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct tg3 *tp = netdev_priv(dev); - if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { - /* These are the only valid advertisement bits allowed. */ - if (cmd->autoneg == AUTONEG_ENABLE && - (cmd->advertising & ~(ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full | - ADVERTISED_Autoneg | - ADVERTISED_FIBRE))) - return -EINVAL; - /* Fiber can only do SPEED_1000. */ - else if ((cmd->autoneg != AUTONEG_ENABLE) && - (cmd->speed != SPEED_1000)) - return -EINVAL; - /* Copper cannot force SPEED_1000. */ - } else if ((cmd->autoneg != AUTONEG_ENABLE) && - (cmd->speed == SPEED_1000)) + if (cmd->autoneg != AUTONEG_ENABLE && + cmd->autoneg != AUTONEG_DISABLE) return -EINVAL; - else if ((cmd->speed == SPEED_1000) && - (tp->tg3_flags & TG3_FLAG_10_100_ONLY)) + + if (cmd->autoneg == AUTONEG_DISABLE && + cmd->duplex != DUPLEX_FULL && + cmd->duplex != DUPLEX_HALF) return -EINVAL; + if (cmd->autoneg == AUTONEG_ENABLE) { + u32 mask = ADVERTISED_Autoneg | + ADVERTISED_Pause | + ADVERTISED_Asym_Pause; + + if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY)) + mask |= ADVERTISED_1000baseT_Half | + ADVERTISED_1000baseT_Full; + + if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) + mask |= ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_TP; + else + mask |= ADVERTISED_FIBRE; + + if (cmd->advertising & ~mask) + return -EINVAL; + + mask &= (ADVERTISED_1000baseT_Half | + ADVERTISED_1000baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full); + + cmd->advertising &= mask; + } else { + if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { + if (cmd->speed != SPEED_1000) + return -EINVAL; + + if (cmd->duplex != DUPLEX_FULL) + return -EINVAL; + } else { + if (cmd->speed != SPEED_100 && + cmd->speed != SPEED_10) + return -EINVAL; + } + } + tg3_full_lock(tp, 0); tp->link_config.autoneg = cmd->autoneg; @@ -9079,12 +9270,12 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; - if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) + if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) epause->rx_pause = 1; else epause->rx_pause = 0; - if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) + if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) epause->tx_pause = 1; else epause->tx_pause = 0; @@ -9107,13 +9298,13 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam else tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; if (epause->rx_pause) - tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX; + tp->link_config.flowctrl |= FLOW_CTRL_RX; else - tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX; + tp->link_config.flowctrl &= ~FLOW_CTRL_RX; if (epause->tx_pause) - tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX; + tp->link_config.flowctrl |= FLOW_CTRL_TX; else - tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX; + tp->link_config.flowctrl &= ~FLOW_CTRL_TX; if (netif_running(dev)) { tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); @@ -9244,10 +9435,13 @@ static void tg3_get_ethtool_stats (struct net_device *dev, static int tg3_test_nvram(struct tg3 *tp) { u32 csum, magic; - __le32 *buf; + __be32 *buf; int i, j, k, err = 0, size; - if (tg3_nvram_read_swab(tp, 0, &magic) != 0) + if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) + return 0; + + if (tg3_nvram_read(tp, 0, &magic) != 0) return -EIO; if (magic == TG3_EEPROM_MAGIC) @@ -9281,14 +9475,15 @@ static int tg3_test_nvram(struct tg3 *tp) err = -EIO; for (i = 0, j = 0; i < size; i += 4, j++) { - if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0) + err = tg3_nvram_read_be32(tp, i, &buf[j]); + if (err) break; } if (i < size) goto out; /* Selfboot format */ - magic = swab32(le32_to_cpu(buf[0])); + magic = be32_to_cpu(buf[0]); if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { u8 *buf8 = (u8 *) buf, csum8 = 0; @@ -9317,7 +9512,7 @@ static int tg3_test_nvram(struct tg3 *tp) if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) { u8 data[NVRAM_SELFBOOT_DATA_SIZE]; - u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; + u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; u8 *buf8 = (u8 *) buf; /* Separate the parity bits and the data bytes. */ @@ -9360,13 +9555,13 @@ static int tg3_test_nvram(struct tg3 *tp) /* Bootstrap checksum at offset 0x10 */ csum = calc_crc((unsigned char *) buf, 0x10); - if(csum != le32_to_cpu(buf[0x10/4])) + if (csum != be32_to_cpu(buf[0x10/4])) goto out; /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); - if (csum != le32_to_cpu(buf[0xfc/4])) - goto out; + if (csum != be32_to_cpu(buf[0xfc/4])) + goto out; err = 0; @@ -9731,14 +9926,16 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { u32 phytest; - if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) { - u32 phy; + if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { + u32 phy, reg = MII_TG3_FET_SHDW_AUXSTAT2; - tg3_writephy(tp, MII_TG3_EPHY_TEST, - phytest | MII_TG3_EPHY_SHADOW_EN); - if (!tg3_readphy(tp, 0x1b, &phy)) - tg3_writephy(tp, 0x1b, phy & ~0x20); - tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest); + tg3_writephy(tp, MII_TG3_FET_TEST, + phytest | MII_TG3_FET_SHADOW_EN); + if (!tg3_readphy(tp, reg, &phy)) { + phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; + tg3_writephy(tp, reg, phy); + } + tg3_writephy(tp, MII_TG3_FET_TEST, phytest); } val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; } else @@ -9752,7 +9949,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) - tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); + tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); mac_mode |= MAC_MODE_PORT_MODE_MII; } else mac_mode |= MAC_MODE_PORT_MODE_GMII; @@ -10068,8 +10265,12 @@ static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) { struct tg3 *tp = netdev_priv(dev); - if (netif_running(dev)) - tg3_netif_stop(tp); + if (!netif_running(dev)) { + tp->vlgrp = grp; + return; + } + + tg3_netif_stop(tp); tg3_full_lock(tp, 0); @@ -10078,8 +10279,7 @@ static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ __tg3_set_rx_mode(dev); - if (netif_running(dev)) - tg3_netif_start(tp); + tg3_netif_start(tp); tg3_full_unlock(tp); } @@ -10191,7 +10391,7 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) tp->nvram_size = EEPROM_CHIP_SIZE; - if (tg3_nvram_read_swab(tp, 0, &magic) != 0) + if (tg3_nvram_read(tp, 0, &magic) != 0) return; if ((magic != TG3_EEPROM_MAGIC) && @@ -10207,7 +10407,7 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) cursize = 0x10; while (cursize < tp->nvram_size) { - if (tg3_nvram_read_swab(tp, cursize, &val) != 0) + if (tg3_nvram_read(tp, cursize, &val) != 0) return; if (val == magic) @@ -10223,7 +10423,8 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) { u32 val; - if (tg3_nvram_read_swab(tp, 0, &val) != 0) + if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || + tg3_nvram_read(tp, 0, &val) != 0) return; /* Selfboot format */ @@ -10234,7 +10435,18 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) if (tg3_nvram_read(tp, 0xf0, &val) == 0) { if (val != 0) { - tp->nvram_size = (val >> 16) * 1024; + /* This is confusing. We want to operate on the + * 16-bit value at offset 0xf2. The tg3_nvram_read() + * call will read from NVRAM and byteswap the data + * according to the byteswapping settings for all + * other register accesses. This ensures the data we + * want will always reside in the lower 16-bits. + * However, the data in NVRAM is in LE format, which + * means the data from the NVRAM read will always be + * opposite the endianness of the CPU. The 16-bit + * byteswap then brings the data to CPU endianness. + */ + tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; return; } } @@ -10594,6 +10806,7 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) } break; default: + tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; return; } @@ -10685,141 +10898,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) } } -static int tg3_nvram_read_using_eeprom(struct tg3 *tp, - u32 offset, u32 *val) -{ - u32 tmp; - int i; - - if (offset > EEPROM_ADDR_ADDR_MASK || - (offset % 4) != 0) - return -EINVAL; - - tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | - EEPROM_ADDR_DEVID_MASK | - EEPROM_ADDR_READ); - tw32(GRC_EEPROM_ADDR, - tmp | - (0 << EEPROM_ADDR_DEVID_SHIFT) | - ((offset << EEPROM_ADDR_ADDR_SHIFT) & - EEPROM_ADDR_ADDR_MASK) | - EEPROM_ADDR_READ | EEPROM_ADDR_START); - - for (i = 0; i < 1000; i++) { - tmp = tr32(GRC_EEPROM_ADDR); - - if (tmp & EEPROM_ADDR_COMPLETE) - break; - msleep(1); - } - if (!(tmp & EEPROM_ADDR_COMPLETE)) - return -EBUSY; - - *val = tr32(GRC_EEPROM_DATA); - return 0; -} - -#define NVRAM_CMD_TIMEOUT 10000 - -static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) -{ - int i; - - tw32(NVRAM_CMD, nvram_cmd); - for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { - udelay(10); - if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { - udelay(10); - break; - } - } - if (i == NVRAM_CMD_TIMEOUT) { - return -EBUSY; - } - return 0; -} - -static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) -{ - if ((tp->tg3_flags & TG3_FLAG_NVRAM) && - (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && - (tp->tg3_flags2 & TG3_FLG2_FLASH) && - !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && - (tp->nvram_jedecnum == JEDEC_ATMEL)) - - addr = ((addr / tp->nvram_pagesize) << - ATMEL_AT45DB0X1B_PAGE_POS) + - (addr % tp->nvram_pagesize); - - return addr; -} - -static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) -{ - if ((tp->tg3_flags & TG3_FLAG_NVRAM) && - (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && - (tp->tg3_flags2 & TG3_FLG2_FLASH) && - !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && - (tp->nvram_jedecnum == JEDEC_ATMEL)) - - addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * - tp->nvram_pagesize) + - (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); - - return addr; -} - -static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) -{ - int ret; - - if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) - return tg3_nvram_read_using_eeprom(tp, offset, val); - - offset = tg3_nvram_phys_addr(tp, offset); - - if (offset > NVRAM_ADDR_MSK) - return -EINVAL; - - ret = tg3_nvram_lock(tp); - if (ret) - return ret; - - tg3_enable_nvram_access(tp); - - tw32(NVRAM_ADDR, offset); - ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | - NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); - - if (ret == 0) - *val = swab32(tr32(NVRAM_RDDATA)); - - tg3_disable_nvram_access(tp); - - tg3_nvram_unlock(tp); - - return ret; -} - -static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) -{ - u32 v; - int res = tg3_nvram_read(tp, offset, &v); - if (!res) - *val = cpu_to_le32(v); - return res; -} - -static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) -{ - int err; - u32 tmp; - - err = tg3_nvram_read(tp, offset, &tmp); - *val = swab32(tmp); - return err; -} - static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, u32 offset, u32 len, u8 *buf) { @@ -10828,13 +10906,19 @@ static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, for (i = 0; i < len; i += 4) { u32 addr; - __le32 data; + __be32 data; addr = offset + i; memcpy(&data, buf + i, 4); - tw32(GRC_EEPROM_DATA, le32_to_cpu(data)); + /* + * The SEEPROM interface expects the data to always be opposite + * the native endian format. We accomplish this by reversing + * all the operations that would have been performed on the + * data from a call to tg3_nvram_read_be32(). + */ + tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); val = tr32(GRC_EEPROM_ADDR); tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); @@ -10884,8 +10968,9 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, phy_addr = offset & ~pagemask; for (j = 0; j < pagesize; j += 4) { - if ((ret = tg3_nvram_read_le(tp, phy_addr + j, - (__le32 *) (tmp + j)))) + ret = tg3_nvram_read_be32(tp, phy_addr + j, + (__be32 *) (tmp + j)); + if (ret) break; } if (ret) @@ -10932,7 +11017,6 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, __be32 data; data = *((__be32 *) (tmp + j)); - /* swab32(le32_to_cpu(data)), actually */ tw32(NVRAM_WRDATA, be32_to_cpu(data)); tw32(NVRAM_ADDR, phy_addr + j); @@ -11388,7 +11472,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp) int err; /* Reading the PHY ID register can conflict with ASF - * firwmare access to the PHY hardware. + * firmware access to the PHY hardware. */ err = 0; if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || @@ -11511,24 +11595,26 @@ skip_phy_reset: static void __devinit tg3_read_partno(struct tg3 *tp) { - unsigned char vpd_data[256]; + unsigned char vpd_data[256]; /* in little-endian format */ unsigned int i; u32 magic; - if (tg3_nvram_read_swab(tp, 0x0, &magic)) + if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || + tg3_nvram_read(tp, 0x0, &magic)) goto out_not_found; if (magic == TG3_EEPROM_MAGIC) { for (i = 0; i < 256; i += 4) { u32 tmp; - if (tg3_nvram_read(tp, 0x100 + i, &tmp)) + /* The data is in little-endian format in NVRAM. + * Use the big-endian read routines to preserve + * the byte order as it exists in NVRAM. + */ + if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp)) goto out_not_found; - vpd_data[i + 0] = ((tmp >> 0) & 0xff); - vpd_data[i + 1] = ((tmp >> 8) & 0xff); - vpd_data[i + 2] = ((tmp >> 16) & 0xff); - vpd_data[i + 3] = ((tmp >> 24) & 0xff); + memcpy(&vpd_data[i], &tmp, sizeof(tmp)); } } else { int vpd_cap; @@ -11554,7 +11640,7 @@ static void __devinit tg3_read_partno(struct tg3 *tp) pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA, &tmp); v = cpu_to_le32(tmp); - memcpy(&vpd_data[i], &v, 4); + memcpy(&vpd_data[i], &v, sizeof(v)); } } @@ -11606,6 +11692,18 @@ static void __devinit tg3_read_partno(struct tg3 *tp) out_not_found: if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) strcpy(tp->board_part_number, "BCM95906"); + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && + tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) + strcpy(tp->board_part_number, "BCM57780"); + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && + tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) + strcpy(tp->board_part_number, "BCM57760"); + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && + tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) + strcpy(tp->board_part_number, "BCM57790"); + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && + tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) + strcpy(tp->board_part_number, "BCM57788"); else strcpy(tp->board_part_number, "none"); } @@ -11614,15 +11712,79 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) { u32 val; - if (tg3_nvram_read_swab(tp, offset, &val) || + if (tg3_nvram_read(tp, offset, &val) || (val & 0xfc000000) != 0x0c000000 || - tg3_nvram_read_swab(tp, offset + 4, &val) || + tg3_nvram_read(tp, offset + 4, &val) || val != 0) return 0; return 1; } +static void __devinit tg3_read_bc_ver(struct tg3 *tp) +{ + u32 val, offset, start, ver_offset; + int i; + bool newver = false; + + if (tg3_nvram_read(tp, 0xc, &offset) || + tg3_nvram_read(tp, 0x4, &start)) + return; + + offset = tg3_nvram_logical_addr(tp, offset); + + if (tg3_nvram_read(tp, offset, &val)) + return; + + if ((val & 0xfc000000) == 0x0c000000) { + if (tg3_nvram_read(tp, offset + 4, &val)) + return; + + if (val == 0) + newver = true; + } + + if (newver) { + if (tg3_nvram_read(tp, offset + 8, &ver_offset)) + return; + + offset = offset + ver_offset - start; + for (i = 0; i < 16; i += 4) { + __be32 v; + if (tg3_nvram_read_be32(tp, offset + i, &v)) + return; + + memcpy(tp->fw_ver + i, &v, sizeof(v)); + } + } else { + u32 major, minor; + + if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) + return; + + major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> + TG3_NVM_BCVER_MAJSFT; + minor = ver_offset & TG3_NVM_BCVER_MINMSK; + snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); + } +} + +static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) +{ + u32 val, major, minor; + + /* Use native endian representation */ + if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) + return; + + major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> + TG3_NVM_HWSB_CFG1_MAJSFT; + minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> + TG3_NVM_HWSB_CFG1_MINSFT; + + snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); +} + static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) { u32 offset, major, minor, build; @@ -11648,7 +11810,7 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) return; } - if (tg3_nvram_read_swab(tp, offset, &val)) + if (tg3_nvram_read(tp, offset, &val)) return; build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> @@ -11668,49 +11830,15 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) } } -static void __devinit tg3_read_fw_ver(struct tg3 *tp) +static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) { u32 val, offset, start; - u32 ver_offset; - int i, bcnt; - - if (tg3_nvram_read_swab(tp, 0, &val)) - return; - - if (val != TG3_EEPROM_MAGIC) { - if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) - tg3_read_sb_ver(tp, val); - - return; - } - - if (tg3_nvram_read_swab(tp, 0xc, &offset) || - tg3_nvram_read_swab(tp, 0x4, &start)) - return; - - offset = tg3_nvram_logical_addr(tp, offset); - - if (!tg3_fw_img_is_valid(tp, offset) || - tg3_nvram_read_swab(tp, offset + 8, &ver_offset)) - return; - - offset = offset + ver_offset - start; - for (i = 0; i < 16; i += 4) { - __le32 v; - if (tg3_nvram_read_le(tp, offset + i, &v)) - return; - - memcpy(tp->fw_ver + i, &v, 4); - } - - if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || - (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) - return; + int i, vlen; for (offset = TG3_NVM_DIR_START; offset < TG3_NVM_DIR_END; offset += TG3_NVM_DIRENT_SIZE) { - if (tg3_nvram_read_swab(tp, offset, &val)) + if (tg3_nvram_read(tp, offset, &val)) return; if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) @@ -11722,37 +11850,97 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) start = 0x08000000; - else if (tg3_nvram_read_swab(tp, offset - 4, &start)) + else if (tg3_nvram_read(tp, offset - 4, &start)) return; - if (tg3_nvram_read_swab(tp, offset + 4, &offset) || + if (tg3_nvram_read(tp, offset + 4, &offset) || !tg3_fw_img_is_valid(tp, offset) || - tg3_nvram_read_swab(tp, offset + 8, &val)) + tg3_nvram_read(tp, offset + 8, &val)) return; offset += val - start; - bcnt = strlen(tp->fw_ver); + vlen = strlen(tp->fw_ver); - tp->fw_ver[bcnt++] = ','; - tp->fw_ver[bcnt++] = ' '; + tp->fw_ver[vlen++] = ','; + tp->fw_ver[vlen++] = ' '; for (i = 0; i < 4; i++) { - __le32 v; - if (tg3_nvram_read_le(tp, offset, &v)) + __be32 v; + if (tg3_nvram_read_be32(tp, offset, &v)) return; offset += sizeof(v); - if (bcnt > TG3_VER_SIZE - sizeof(v)) { - memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt); + if (vlen > TG3_VER_SIZE - sizeof(v)) { + memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); break; } - memcpy(&tp->fw_ver[bcnt], &v, sizeof(v)); - bcnt += sizeof(v); + memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); + vlen += sizeof(v); + } +} + +static void __devinit tg3_read_dash_ver(struct tg3 *tp) +{ + int vlen; + u32 apedata; + + if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || + !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) + return; + + apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); + if (apedata != APE_SEG_SIG_MAGIC) + return; + + apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); + if (!(apedata & APE_FW_STATUS_READY)) + return; + + apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); + + vlen = strlen(tp->fw_ver); + + snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d", + (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, + (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, + (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, + (apedata & APE_FW_VERSION_BLDMSK)); +} + + +static void __devinit tg3_read_fw_ver(struct tg3 *tp) +{ + u32 val; + + if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { + tp->fw_ver[0] = 's'; + tp->fw_ver[1] = 'b'; + tp->fw_ver[2] = '\0'; + + return; } + if (tg3_nvram_read(tp, 0, &val)) + return; + + if (val == TG3_EEPROM_MAGIC) + tg3_read_bc_ver(tp); + else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) + tg3_read_sb_ver(tp, val); + else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) + tg3_read_hwsb_ver(tp); + else + return; + + if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || + (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) + return; + + tg3_read_mgmtfw_ver(tp); + tp->fw_ver[TG3_VER_SIZE - 1] = 0; } @@ -11770,7 +11958,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) { }, }; u32 misc_ctrl_reg; - u32 cacheline_sz_reg; u32 pci_state_reg, grc_misc_cfg; u32 val; u16 pci_cmd; @@ -11944,14 +12131,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); - pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ, - &cacheline_sz_reg); - - tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff; - tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff; - tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff; - tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) tp->pdev_peer = tg3_find_peer(tp); @@ -12021,7 +12200,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) + tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || + tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; } } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { @@ -12049,17 +12229,17 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; + pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, + &tp->pci_cacheline_sz); + pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, + &tp->pci_lat_timer); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && tp->pci_lat_timer < 64) { tp->pci_lat_timer = 64; - cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0); - cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8); - cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16); - cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24); - - pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ, - cacheline_sz_reg); + pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, + tp->pci_lat_timer); } if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { @@ -12215,7 +12395,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; - if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) { + if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || + tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { /* Turn off the debug UART. */ tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) @@ -12316,6 +12497,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) tp->coalesce_mode |= HOSTCC_MODE_32BYTE; + if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 && + tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) || + tp->pci_chip_rev_id == CHIPREV_ID_57780_A0) + tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD; + /* Initialize data/descriptor byte/word swapping. */ val = tr32(GRC_MODE); val &= GRC_MODE_HOST_STACKUP; @@ -12549,14 +12735,11 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) } if (!addr_ok) { /* Next, try NVRAM. */ - if (!tg3_nvram_read(tp, mac_offset + 0, &hi) && - !tg3_nvram_read(tp, mac_offset + 4, &lo)) { - dev->dev_addr[0] = ((hi >> 16) & 0xff); - dev->dev_addr[1] = ((hi >> 24) & 0xff); - dev->dev_addr[2] = ((lo >> 0) & 0xff); - dev->dev_addr[3] = ((lo >> 8) & 0xff); - dev->dev_addr[4] = ((lo >> 16) & 0xff); - dev->dev_addr[5] = ((lo >> 24) & 0xff); + if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && + !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && + !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { + memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); + memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); } /* Finally just fetch it out of the MAC control regs. */ else { @@ -13326,17 +13509,17 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, * do DMA address check in tg3_start_xmit(). */ if (tp->tg3_flags2 & TG3_FLG2_IS_5788) - persist_dma_mask = dma_mask = DMA_32BIT_MASK; + persist_dma_mask = dma_mask = DMA_BIT_MASK(32); else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { - persist_dma_mask = dma_mask = DMA_40BIT_MASK; + persist_dma_mask = dma_mask = DMA_BIT_MASK(40); #ifdef CONFIG_HIGHMEM - dma_mask = DMA_64BIT_MASK; + dma_mask = DMA_BIT_MASK(64); #endif } else - persist_dma_mask = dma_mask = DMA_64BIT_MASK; + persist_dma_mask = dma_mask = DMA_BIT_MASK(64); /* Configure DMA attributes. */ - if (dma_mask > DMA_32BIT_MASK) { + if (dma_mask > DMA_BIT_MASK(32)) { err = pci_set_dma_mask(pdev, dma_mask); if (!err) { dev->features |= NETIF_F_HIGHDMA; @@ -13349,8 +13532,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, } } } - if (err || dma_mask == DMA_32BIT_MASK) { - err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); + if (err || dma_mask == DMA_BIT_MASK(32)) { + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (err) { printk(KERN_ERR PFX "No usable DMA configuration, " "aborting.\n"); @@ -13423,6 +13606,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, } tg3_ape_lock_init(tp); + + if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) + tg3_read_dash_ver(tp); } /* @@ -13457,7 +13643,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, /* flow control autonegotiation is default behavior */ tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; - tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX; + tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; tg3_init_coal(tp); @@ -13495,8 +13681,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", dev->name, tp->dma_rwctrl, - (pdev->dma_mask == DMA_32BIT_MASK) ? 32 : - (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64)); + (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 : + (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64)); return 0; diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index ed4d1bf..32f16ef 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -43,28 +43,9 @@ #define TG3PCI_DEVICE_TIGON3_57780 0x1692 #define TG3PCI_DEVICE_TIGON3_57760 0x1690 #define TG3PCI_DEVICE_TIGON3_57790 0x1694 -#define TG3PCI_DEVICE_TIGON3_57720 0x168c +#define TG3PCI_DEVICE_TIGON3_57788 0x1691 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 -#define TG3PCI_COMMAND 0x00000004 -#define TG3PCI_STATUS 0x00000006 -#define TG3PCI_CCREVID 0x00000008 -#define TG3PCI_CACHELINESZ 0x0000000c -#define TG3PCI_LATTIMER 0x0000000d -#define TG3PCI_HEADERTYPE 0x0000000e -#define TG3PCI_BIST 0x0000000f -#define TG3PCI_BASE0_LOW 0x00000010 -#define TG3PCI_BASE0_HIGH 0x00000014 -/* 0x18 --> 0x2c unused */ -#define TG3PCI_SUBSYSVENID 0x0000002c -#define TG3PCI_SUBSYSID 0x0000002e -#define TG3PCI_ROMADDR 0x00000030 -#define TG3PCI_CAPLIST 0x00000034 -/* 0x35 --> 0x3c unused */ -#define TG3PCI_IRQ_LINE 0x0000003c -#define TG3PCI_IRQ_PIN 0x0000003d -#define TG3PCI_MIN_GNT 0x0000003e -#define TG3PCI_MAX_LAT 0x0000003f -/* 0x40 --> 0x64 unused */ +/* 0x04 --> 0x64 unused */ #define TG3PCI_MSI_DATA 0x00000064 /* 0x66 --> 0x68 unused */ #define TG3PCI_MISC_HOST_CTRL 0x00000068 @@ -115,10 +96,8 @@ #define CHIPREV_ID_5752_A1 0x6001 #define CHIPREV_ID_5714_A2 0x9002 #define CHIPREV_ID_5906_A1 0xc001 -#define CHIPREV_ID_5784_A0 0x5784000 -#define CHIPREV_ID_5784_A1 0x5784001 -#define CHIPREV_ID_5761_A0 0x5761000 -#define CHIPREV_ID_5761_A1 0x5761001 +#define CHIPREV_ID_57780_A0 0x57780000 +#define CHIPREV_ID_57780_A1 0x57780001 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define ASIC_REV_5700 0x07 #define ASIC_REV_5701 0x00 @@ -236,9 +215,11 @@ #define DUAL_MAC_CTRL_ID 0x00000004 #define TG3PCI_PRODID_ASICREV 0x000000bc #define PROD_ID_ASIC_REV_MASK 0x0fffffff -/* 0xc0 --> 0x100 unused */ +/* 0xc0 --> 0x110 unused */ -/* 0x100 --> 0x200 unused */ +#define TG3_CORR_ERR_STAT 0x00000110 +#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff +/* 0x114 --> 0x200 unused */ /* Mailbox registers */ #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ @@ -886,6 +867,7 @@ #define RCVLPC_STATSCTRL_ENABLE 0x00000001 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 #define RCVLPC_STATS_ENABLE 0x00002018 +#define RCVLPC_STATSENAB_ASF_FIX 0x00000002 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 #define RCVLPC_STATS_INCMASK 0x0000201c @@ -1716,9 +1698,23 @@ #define PCIE_TRANSACTION_CFG 0x00007c04 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 #define PCIE_TRANS_CFG_LOM 0x00000020 +/* 0x7c08 --> 0x7d28 unused */ #define PCIE_PWR_MGMT_THRESH 0x00007d28 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 +#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 +#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 +/* 0x7d2c --> 0x7d54 unused */ + +#define TG3_PCIE_LNKCTL 0x00007d54 +#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 +#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 +/* 0x7d58 --> 0x7e70 unused */ + +#define TG3_PCIE_EIDLE_DELAY 0x00007e70 +#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f +#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c +/* 0x7e74 --> 0x8000 unused */ /* OTP bit definitions */ @@ -1763,6 +1759,13 @@ #define TG3_OTP_DEFAULT 0x286c1640 +/* Hardware Selfboot NVRAM layout */ +#define TG3_NVM_HWSB_CFG1 0x00000004 +#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 +#define TG3_NVM_HWSB_CFG1_MAJSFT 27 +#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 +#define TG3_NVM_HWSB_CFG1_MINSFT 22 + #define TG3_EEPROM_MAGIC 0x669955aa #define TG3_EEPROM_MAGIC_FW 0xa5000000 @@ -1781,6 +1784,10 @@ #define TG3_NVM_DIRENT_SIZE 0xc #define TG3_NVM_DIRTYPE_SHIFT 24 #define TG3_NVM_DIRTYPE_ASFINI 1 +#define TG3_NVM_PTREV_BCVER 0x94 +#define TG3_NVM_BCVER_MAJMSK 0x0000ff00 +#define TG3_NVM_BCVER_MAJSFT 8 +#define TG3_NVM_BCVER_MINMSK 0x000000ff #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 @@ -1926,7 +1933,6 @@ #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ -#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */ #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ #define MII_TG3_DSP_TAP1 0x0001 @@ -1968,12 +1974,6 @@ #define MII_TG3_ISTAT 0x1a /* IRQ status register */ #define MII_TG3_IMASK 0x1b /* IRQ mask register */ -#define MII_TG3_MISC_SHDW 0x1c -#define MII_TG3_MISC_SHDW_WREN 0x8000 -#define MII_TG3_MISC_SHDW_APD_SEL 0x2800 - -#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 - /* ISTAT/IMASK event bits */ #define MII_TG3_INT_LINKCHG 0x0002 #define MII_TG3_INT_SPEEDCHG 0x0004 @@ -1982,7 +1982,9 @@ #define MII_TG3_MISC_SHDW 0x1c #define MII_TG3_MISC_SHDW_WREN 0x8000 -#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 + +#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 +#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 @@ -1990,9 +1992,8 @@ #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 +#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 -#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 -#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 #define MII_TG3_MISC_SHDW 0x1c #define MII_TG3_MISC_SHDW_WREN 0x8000 @@ -2008,12 +2009,6 @@ #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 -#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ -#define MII_TG3_EPHY_SHADOW_EN 0x80 - -#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */ -#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000 - #define MII_TG3_TEST1 0x1e #define MII_TG3_TEST1_TRIM_EN 0x0010 #define MII_TG3_TEST1_CRC_EN 0x8000 @@ -2029,6 +2024,19 @@ #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 + + +/* Fast Ethernet Tranceiver definitions */ +#define MII_TG3_FET_PTEST 0x17 +#define MII_TG3_FET_TEST 0x1f +#define MII_TG3_FET_SHADOW_EN 0x0080 + +#define MII_TG3_FET_SHDW_MISCCTRL 0x10 +#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 + +#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b +#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 + /* APE registers. Accessible through BAR1 */ #define TG3_APE_EVENT 0x000c #define APE_EVENT_1 0x00000001 @@ -2042,6 +2050,14 @@ /* APE shared memory. Accessible through BAR1 */ #define TG3_APE_FW_STATUS 0x400c #define APE_FW_STATUS_READY 0x00000100 +#define TG3_APE_FW_VERSION 0x4018 +#define APE_FW_VERSION_MAJMSK 0xff000000 +#define APE_FW_VERSION_MAJSFT 24 +#define APE_FW_VERSION_MINMSK 0x00ff0000 +#define APE_FW_VERSION_MINSFT 16 +#define APE_FW_VERSION_REVMSK 0x0000ff00 +#define APE_FW_VERSION_REVSFT 8 +#define APE_FW_VERSION_BLDMSK 0x000000ff #define TG3_APE_HOST_SEG_SIG 0x4200 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 #define TG3_APE_HOST_SEG_LEN 0x4204 @@ -2388,8 +2404,6 @@ struct tg3_link_config { u8 duplex; u8 autoneg; u8 flowctrl; -#define TG3_FLOW_CTRL_TX 0x01 -#define TG3_FLOW_CTRL_RX 0x02 /* Describes what we actually have. */ u8 active_flowctrl; @@ -2727,7 +2741,8 @@ struct tg3 { #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 #define TG3_FLG3_5755_PLUS 0x00002000 #define TG3_FLG3_NO_NVRAM 0x00004000 -#define TG3_FLG3_PHY_IS_FET 0x00008000 +#define TG3_FLG3_PHY_IS_FET 0x00007fff +#define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000 struct timer_list timer; u16 timer_counter; @@ -2759,10 +2774,9 @@ struct tg3 { /* PCI block */ u32 pci_chip_rev_id; + u16 pci_cmd; u8 pci_cacheline_sz; u8 pci_lat_timer; - u8 pci_hdr_type; - u8 pci_bist; u32 pci_cfg_state[64 / sizeof(u32)]; int pm_cap; @@ -2808,7 +2822,6 @@ struct tg3 { u32 led_ctrl; u32 phy_otp; - u16 pci_cmd; char board_part_number[24]; #define TG3_VER_SIZE 32