From: Prarit Bhargava <prarit@redhat.com> Date: Fri, 14 Aug 2009 08:03:36 -0400 Subject: [misc] support Intel multi-APIC-cluster systems Message-id: 4A855298.3000901@redhat.com O-Subject: Re: [RHEL5.5 PATCH] Support Intel multi-APIC-cluster systems Bugzilla: 507333 RH-Acked-by: Dean Nelson <dnelson@redhat.com> RH-Acked-by: Luming Yu <luyu@redhat.com> RH-Acked-by: John Feeney <jfeeney@redhat.com> Backport of upstream e0e42142bab96404de535cceb85d6533d5ad7942. Introduces apic_cluster_num which returns the number of APIC clusters, and uses a dmi_check in apic_is_clustered to check whether or not the TSC is unstable. This change has been brought around because Intel now has multi-APIC cluster systems (Nehalem-EX). This patch also maintains the AMD WAR introduced in RHEL5 commit fc43348c2160ed3ec646bb6f5b737a89674330c2. Successfully compiled and tested by me. Resolves BZ 507333. Patch updated with dnelson's comments. P. diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c index de9f6a4..9a82ceb 100644 --- a/arch/x86_64/kernel/apic.c +++ b/arch/x86_64/kernel/apic.c @@ -19,6 +19,7 @@ #include <linux/mm.h> #include <linux/delay.h> #include <linux/bootmem.h> +#include <linux/dmi.h> #include <linux/smp_lock.h> #include <linux/interrupt.h> #include <linux/mc146818rtc.h> @@ -1025,16 +1026,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs) irq_exit(); } -/* - * apic_is_clustered_box() -- Check if we can expect good TSC - * - * Thus far, the major user of this is IBM's Summit2 series: - * - * Clustered boxes may have unsynced TSC problems if they are - * multi-chassis. Use available data to take a good guess. - * If in doubt, go HPET. - */ -__cpuinit int apic_is_clustered_box(void) +static int __cpuinit apic_cluster_num(void) { int i, clusters, zeros; unsigned id; @@ -1073,12 +1065,68 @@ __cpuinit int apic_is_clustered_box(void) ++zeros; } + return clusters; +} + + +static int __cpuinitdata multi_checked; +static int __cpuinitdata multi; + +static int __cpuinit set_multi(struct dmi_system_id *d) +{ + if (multi) + return 0; + printk(KERN_INFO "APIC: %s detected, Multi Chassis\n", d->ident); + multi = 1; + return 0; +} + +static const struct dmi_system_id multi_dmi_table[] = { + { + .callback = set_multi, + .ident = "IBM System Summit2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "IBM"), + DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), + }, + }, + {} +}; + +static void __cpuinit dmi_check_multi(void) +{ + if (multi_checked) + return; + + dmi_check_system(multi_dmi_table); + multi_checked = 1; +} + +/* + * apic_is_clustered_box() -- Check if we can expect good TSC + * + * Thus far, the major user of this is IBM's Summit2 series: + * Clustered boxes may have unsynced TSC problems if they are + * multi-chassis. + * Use DMI to check them + */ +__cpuinit int apic_is_clustered_box(void) +{ + dmi_check_multi(); + if (multi) + return 1; + + if (!is_vsmp_box()) + return 0; + /* - * If clusters > 2, then should be multi-chassis. - * May have to revisit this when multi-core + hyperthreaded CPUs come - * out, but AFAIK this will work even for them. + * ScaleMP vSMPowered boxes have one cluster per board and TSCs are + * not guaranteed to be synced between boards */ - return (clusters > 2); + if (apic_cluster_num() > 1) + return 1; + + return 0; } /*